Dicing method for power transistors

Patent metadata

Field	Value
Publication number	US-2016204074-A1
Application number	US-201514596326-A
Country	US
Kind code	A1
Filing date	Jan 14, 2015
Priority date	Jan 14, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.

First claim

1 - 15 . (canceled)

16 . A method, comprising:
providing a semiconductor wafer comprising a device layer arranged thereover; forming a device structure on or within an upper surface the device layer; forming a crack stop surrounding the device structure, wherein the crack stop is configured to reinforce the semiconductor wafer to limit cracking; using a laser to form a groove along a scribe line outside the crack stop, wherein the groove extends completely through the device layer and into an upper surface region of the semiconductor wafer; and cutting the semiconductor wafer along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die.

17 . The method of claim 16 ,
wherein the groove formed by the laser has a first width; and wherein the cut made by the cutting blade has a second width, which is less than the first width.

18 . The method of claim 17 ,
wherein the first width is about four times larger than a thickness of the device layer; and wherein the second width is about three times larger than the thickness of the device layer.

19 . The method of claim 16 , further comprising:
forming a dielectric layer over the device layer prior forming the groove; and forming the groove through the dielectric layer, wherein the groove establishes a vertical dielectric sidewall and terminates in a rounded, concave, spherical, or tapered surface in the upper surface region of the semiconductor wafer.

20 . The method of claim 16 ,
wherein the crack stop has a first width, and further comprising:
forming an isolation region between an inner edge of the crack stop and the device structure, the isolation region having a second width;
forming the groove a distance away from an outer edge of the crack stop;
wherein the first and second widths are about equal; and
wherein the distance is larger than the first and second widths.

21 . The method of claim 16 ,
wherein the groove establishes a first pair of vertical sidewalls on die regions directly adjacent to the groove, wherein the first pair of vertical sidewalls are spaced apart by a first distance corresponding to a width of the groove and wherein a bottom portion of the groove terminates in a rounded, concave, spherical, or tapered surface in the upper surface region of the semiconductor wafer.

22 . The method of claim 21 , wherein cutting the semiconductor wafer along the grooved scribe line establishes a second pair of vertical sidewalls extending downwardly from the rounded, concave, spherical, or tapered surface, wherein the second pair of vertical sidewalls are spaced apart by a second distance that is less than the first distance.

23 . The method of claim 16 :
wherein the semiconductor wafer comprises a group IV element; and wherein the device layer comprises a group III-V compound.

24 . The method of claim 16 :
wherein the semiconductor wafer is made of silicon; and wherein the device layer is made of GaN.

25 . The method of claim 16 , wherein the crack stop comprises a ring of alternating metallization layers and vias disposed within a dielectric.

26 . A method, comprising:
providing a silicon wafer and a group III-V device layer disposed over an upper surface of the silicon wafer, wherein a plurality of die regions are arranged over the upper surface of the silicon wafer and are separated from one another by scribe lines; forming a crack stop within a die region over the group III-V device layer, wherein the crack stop is configured to reinforce the silicon wafer to limit cracking; using a laser to form a groove along a scribe line of the die region outside an outer perimeter of the crack stop, wherein the groove extends completely through the group III-V device layer and into an upper surface region of the silicon wafer without passing completely through the silicon wafer; and after the laser has been used to form the grooved scribe line, tracing a cutting blade along the grooved scribe line to cut completely through the silicon wafer and singulate the silicon wafer into two or more die regions.

27 . The method of claim 26 :
wherein the groove formed by the laser has a first width; and wherein the cut made by the blade has a second width, which is less than the first width.

28 . The method of claim 27 ,
wherein the first and second widths are each larger than a thickness of the device layer.

29 . The method of claim 26 , further comprising:
forming a dielectric layer over the group III-V device layer prior forming the groove; and using the laser to form the groove through the dielectric layer, wherein the groove establishes a vertical dielectric sidewall and terminates in a rounded, concave, spherical, or tapered surface in the upper surface region of the silicon wafer.

30 . The method of claim 26 ,
wherein the groove establishes a first pair of vertical sidewalls on die regions directly adjacent to the groove, wherein the first pair of vertical sidewalls are spaced apart by a first distance corresponding to a width of the groove and wherein a bottom portion of the groove terminates in a rounded, concave, spherical, or tapered surface in the upper surface region of the silicon wafer.

31 . The method of claim 30 , wherein cutting the silicon wafer along the grooved scribe line establishes a second pair of vertical sidewalls extending downwardly from the rounded, concave, spherical, or tapered surface, wherein the second pair of vertical sidewalls are spaced apart by a second distance that is less than the first distance.

32 . The method of claim 26 , further comprising:
forming a dielectric layer over the group III-V device layer, wherein the groove formed by the laser extends completely through the dielectric layer as well as through the group III-V device layer.

33 . The method of claim 26 , wherein the group III-V device layer comprises gallium nitride (GaN).

34 . The method of claim 26 wherein the crack stop is rectangular.

35 . The method of claim 26 , further comprising forming a layer of aluminum gallium nitride (AlGaN) between an upper surface of the group III-V device layer and the crack stop.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yu-Syuan
• Yu Jiun-Lei Jerry
• Lin Ming-Cheng
• Huang Hsin-Chieh
• Wang Chao-Hsiung

Classifications

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title