Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes
US-2018374753-A1 · Dec 27, 2018 · US
of three-or-more electrode devices
of three-or-more electrode devices · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D48/031 |
| Official title | {of three-or-more electrode devices} |
| Display label | of three-or-more electrode devices |
| Total patents | 172 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 17 |
| 2016 | 16 |
| 2017 | 16 |
| 2018 | 28 |
| 2019 | 32 |
| 2020 | 19 |
| 2021 | 13 |
| 2022 | 8 |
| 2023 | 5 |
| 2024 | 4 |
| 2025 | 11 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Transistor with fluorinated graphene spacer
US-2018342585-A1 · Nov 29, 2018 · US
Semiconductor device
US-2018342578-A1 · Nov 29, 2018 · US
Metal gates of transistors having reduced resistivity
US-10141225-B2 · Nov 27, 2018 · US
Metal Gates of Transistors Having Reduced Resistivity
US-2018315652-A1 · Nov 1, 2018 · US
Semiconductor device and method of manufacturing the same
US-10079282-B2 · Sep 18, 2018 · US
Surface modified diamond materials and methods of manufacturing
US-2018212026-A1 · Jul 26, 2018 · US
Nanoparticle structure and process for manufacture
US-2018200785-A1 · Jul 19, 2018 · US
Poly gate extension source to body contact
US-2018166566-A1 · Jun 14, 2018 · US
Semiconductor device including two-dimensional material
US-9991371-B2 · Jun 5, 2018 · US
Semiconductor structure having multiple-porous graphene layers and the fabrication method thereof
US-2018097066-A1 · Apr 5, 2018 · US
Semiconductor device
US-2017345899-A1 · Nov 30, 2017 · US
Hybrid integration fabrication of nanowire gate-all-around ge pfet and polygonal iii-v pfet cmos device
US-2017271211-A1 · Sep 21, 2017 · US
Fabrication method of silicon carbide semiconductor apparatus and silicon carbide semiconductor apparatus fabricated thereby
US-9768260-B2 · Sep 19, 2017 · US
Method of forming graphene nanopattern by using mask formed from block copolymer
US-9748108-B2 · Aug 29, 2017 · US
Double exponential mechanism controlled transistor
US-9748379-B2 · Aug 29, 2017 · US
Method of forming graphene nanopattern, graphene-containing device, and method of manufacturing the graphene-containing device
US-2017229546-A1 · Aug 10, 2017 · US
Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device
US-9721846-B1 · Aug 1, 2017 · US
Vertical-channel type junction SiC power FET and method of manufacturing same
US-9691908-B2 · Jun 27, 2017 · US
Substrate resistor with overlying gate structure
US-2017162647-A1 · Jun 8, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D48/031?
- CPC H10D48/031 is the Cooperative Patent Classification code for “of three-or-more electrode devices.”
- How many patents are filed under CPC H10D48/031 (of three-or-more electrode devices)?
- Our database includes 172 publications tagged with this CPC code.
- Is patent activity under CPC H10D48/031 growing?
- Publication counts under this code: 4 in 2024 vs 11 in 2025 (latest complete years).