Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10079282-B2
Application number	US-201414473158-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Sep 3, 2013
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an i-type or a p-type first diamond semiconductor layer;
an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer;
a mesa structure including
the first diamond semiconductor layer,
the second diamond semiconductor layer,
a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and
a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane; and
an n-type first diamond semiconductor region provided on the side surface, the first diamond semiconductor region being in contact with the second diamond semiconductor layer and having an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer;
a p-type third diamond semiconductor layer provided on the first diamond semiconductor layer opposite to the second diamond semiconductor layer, the third diamond semiconductor layer having a p-type impurity concentration higher than a p-type impurity concentration of the first diamond semiconductor layer;
a p-type fourth diamond semiconductor layer provided on the second diamond semiconductor layer;
a first electrode electrically connected to the second diamond semiconductor layer, the first electrode provided directly on the second diamond semiconductor layer;
a second electrode electrically connected to the third diamond semiconductor layer, the second electrode provided directly on the third diamond semiconductor layer; and
a third electrode electrically connected to the fourth diamond semiconductor layer, the third electrode provided directly on the fourth diamond semiconductor layer.

2. The device according to claim 1 , further comprising:
a plurality of n-type second diamond semiconductor regions provided on a surface of the first diamond semiconductor layer around the mesa structure, the second diamond semiconductor regions having an n-type impurity concentration lower than the n-type impurity concentration of the second diamond semiconductor layer, the second diamond semiconductor regions being aligned in a [011], [0-11], [0-1-1] or [01-1] direction, the second diamond semiconductor regions extending linearly, one of the second semiconductor regions being separately disposed from one of the other second semiconductor regions.

3. The device according to claim 2 ,
wherein the first diamond semiconductor region and the second diamond semiconductor region are in contact with each other.

4. The device according to claim 2 , therein the second diamond semiconductor regions are provided at the same width and the same interval.

5. The device according to claim 2 , wherein the first diamond semiconductor region and the second diamond semiconductor region are not in contact with each other.

6. The device according to claim 1 ,
wherein n-type impurities of the first diamond semiconductor region are phosphorous (P) and a phosphorus concentration is between 1×10 15 atoms/cm 3 and 5×10 18 atoms/cm 3 inclusive.

7. The device according to claim 1 ,
wherein the side surface has a plane orientation inclined by 45 to 65 degrees with respect to the direction of <011>±20 degrees from the {100} plane.

8. The device according to claim 1 ,
wherein the first diamond semiconductor region is provided on a corner portion of the top surface and the side surface.

9. A semiconductor device comprising:
an i-type or a p-type first diamond semiconductor layer;
an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer;
a mesa structure including
the first diamond semiconductor layer,
the second diamond semiconductor layer,
a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and
a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane;

an n-type first diamond semiconductor region provided on the side surface, the first diamond semiconductor region being in contact with the second diamond semiconductor layer and having an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer;
a plurality of n-type second diamond semiconductor regions provided on a surface of the first diamond semiconductor layer around the mesa structure, the plurality of n-type second diamond semiconductor regions having an n-type impurity concentration lower than the n-type impurity concentration of the second diamond semiconductor layer, the second diamond semiconductor regions provided at the same width and the same interval;
a p-type third diamond semiconductor layer provided on the first diamond semiconductor layer opposite to the second diamond semiconductor layer, the third diamond semiconductor layer having a p-type impurity concentration higher than a p-type impurity concentration of the first diamond semiconductor layer;
a first electrode electrically connected to the second diamond semiconductor layer, the first electrode provided directly on the second diamond semiconductor layer; and
a second electrode electrically connected to the third diamond semiconductor layer, the second electrode provided directly on the third diamond semiconductor layer.

10. The device according to claim 9 , further comprising:
a plurality of n-type second diamond semiconductor regions provided on a surface of the first diamond semiconductor layer around the mesa structure, the second diamond semiconductor regions having an n-type impurity concentration lower than the n-type impurity concentration of the second diamond semiconductor layer, the second diamond semiconductor regions being aligned in a [011], [0-11] [0-1-1] or [01-1] direction, the second diamond semiconductor regions extending linearly, one of the second semiconductor regions being separately disposed from one of the other second semiconductor regions.

11. A semiconductor device comprising:
an i-type or a p-type first diamond semiconductor layer;
an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer;
a mesa structure including
the first diamond semiconductor layer,
the second diamond semiconductor layer,
a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and
a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane;

an n-type first diamond semiconductor region provided on the side surface, the first diamond semiconductor region being in contact with the second diamond semiconductor layer and having an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer;
a plurality of n-type second diamond semiconductor regions provided on a surface of the first diamond semiconductor layer around the mesa structure, the plurality of n-type second diamond semiconductor regions having an n-type impurity concentration lower than the n-type impurity concentration of the second diamond semiconductor layer, the first diamond semiconductor region and the second diamond semiconductor region not being in contact with each other;
a p-type third diamond semiconductor layer provided on the first diamond semiconductor layer opposite to the second diamond semiconductor layer, the third diamond semiconductor layer having a p-type impurity concentration higher than a p-type impurity concentration of the first diamond semiconductor layer;
a first electrode electrically connected to the second diamond semiconductor layer, the first electrode provided directly on the second diamond semiconductor laye

Assignees

• Toshiba Kk

Inventors

• Suzuki Mariko
• Sakai Tadashi
• Ota Chiharu
• Takao Kazuto
• Shinohe Takashi

Classifications

• H10P95/92

  Formation of n- or p-type semiconductors, e.g. doping of graphene · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title