Double exponential mechanism controlled transistor

Patent metadata

Field	Value
Publication number	US-9748379-B2
Application number	US-201514836054-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Jun 25, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.

First claim

What is claimed is:

1. A tunnel field effect transistor (TFET) device, comprising:
a dielectric structure comprising one or more dielectric layers arranged over a substrate;
a conductive gate electrode contacting the dielectric structure;
a conductive source electrode that contacts the substrate at a first position located along a first side of the conductive gate electrode; and
a conductive drain electrode having a bottommost surface that faces the substrate and that directly contacts an upper surface of dielectric structure facing away from the substrate at a second position located along the first side of the conductive gate electrode.

2. The TFET device of claim 1 , further comprising:
a gate dielectric layer having a first thickness vertically arranged between the conductive gate electrode and the substrate; and
a tunnel dielectric layer having a second thickness vertically arranged between the conductive drain electrode and the substrate, wherein the second thickness is less than the first thickness and wherein the tunnel dielectric layer has a first sidewall that contacts a second sidewall of the gate dielectric layer at a location between the conductive gate electrode and the conductive drain electrode.

3. The TFET device of claim 1 , further comprising:
a source contact region arranged within the substrate at a location not underlying the dielectric structure, wherein the conductive source electrode is disposed onto an upper surface of the source contact region.

4. The TFET device of claim 1 , wherein the conductive gate electrode comprises an ‘o’ shape having a curved sidewall that continuously wraps around a periphery of the conductive drain electrode.

5. The TFET device of claim 1 , wherein the conductive drain electrode comprises aluminum.

6. The TFET device of claim 1 , wherein the conductive drain electrode is separated from the conductive gate electrode by a distance in a range of between 100 nm and 10 nm.

7. The TFET device of claim 1 , further comprising:
a fin comprising a same material as the substrate and protruding outward from the substrate; and
wherein the dielectric structure overlies the fin and the conductive drain electrode is arranged onto the dielectric structure and continuously extends from along a first sidewall of the fin to along an opposing second sidewall of the fin.

8. The TFET device of claim 7 , wherein the conductive gate electrode is arranged on a first side of the fin and the conductive source electrode is arranged onto an opposite second side of the fin.

9. The TFET device of claim 1 , wherein the conductive gate electrode is configured to generate an electric field that causes minority charge carriers to laterally diffuse from below the conductive gate electrode to below the conductive drain electrode.

10. A tunnel field effect transistor (TFET) device, comprising:
a semiconductor substrate;
a conductive gate electrode vertically separated from the semiconductor substrate by a gate dielectric layer disposed onto a front-side of the semiconductor substrate;
a conductive source electrode in electrical contact with the semiconductor substrate; and
a conductive drain electrode vertically separated from the semiconductor substrate by a tunnel dielectric layer disposed onto the front-side of the semiconductor substrate, wherein the conductive drain electrode is laterally positioned along a same side of the conductive gate electrode as the conductive source electrode and wherein the conductive drain electrode is configured to generate an electric field that causes majority charge carriers to tunnel through the tunnel dielectric layer at a location directly below the conductive drain electrode.

11. The TFET device of claim 10 , wherein the conductive source electrode is in contact with the front-side of the semiconductor substrate.

12. The TFET device of claim 10 , wherein the conductive source electrode is in contact with a back-side of the semiconductor substrate opposite the front-side of the semiconductor substrate.

13. The TFET device of claim 10 ,
wherein the conductive drain electrode is laterally between the conductive gate electrode and the conductive source electrode; and
wherein the conductive drain electrode is separated from the conductive source electrode and the conductive gate electrode by an inter-level dielectric (ILD) layer.

14. A method of forming a tunnel field effect transistor (TFET) device, comprising:
forming a gate dielectric layer over a substrate;
forming a conductive gate electrode over the gate dielectric layer, wherein the gate dielectric layer continuously extends along a line between a top surface contacting a lower surface of the conductive gate electrode and a bottom surface contacting the substrate;
removing a part of the gate dielectric layer from a location laterally offset from the conductive gate electrode;
forming a tunnel dielectric layer over the substrate at the location laterally offset from the conductive gate electrode after removing the part of the gate dielectric layer;
forming a conductive source electrode that contacts the substrate at a first position located along a first side of the conductive gate electrode; and
forming a conductive drain electrode over the tunnel dielectric layer.

15. The method of claim 14 , further comprising:
removing a part of the tunnel dielectric layer to form an exposed surface of the substrate; and
forming the conductive source electrode in contact with the exposed surface of the substrate.

16. The TFET of claim 10 , wherein the conductive gate electrode is configured to generate a second electric field that adjusts an effective barrier height of the tunnel dielectric layer.

17. The TFET of claim 10 , wherein the conductive gate electrode is configured to generate a second electric field that causes minority charge carriers to move within the semiconductor substrate from below the conductive gate electrode to below the conductive drain electrode and to adjust an effective barrier height of the tunnel dielectric layer.

18. The TFET device of claim 1 , wherein the dielectric structure continuously extends along a line between the bottommost surface of the conductive drain electrode and an upper surface of the substrate facing the bottommost surface of the conductive drain electrode.

19. The TFET device of claim 1 ,
wherein the dielectric structure continuously extends from a first location directly contacting a bottommost surface of the conductive gate electrode facing the substrate to a second location directly contacting the bottommost surface of the conductive drain electrode; and
wherein the dielectric structure has a topmost point at a greatest distance from the substrate that is below the bottommost surface of the conductive gate electrode facing the substrate.

20. The TFET device of claim 1 ,
wherein the dielectric structure continuously extends from a first location directly contacting a bottommost surface of the conductive gate electrode facing the substrate to a second location directly contacting the bottommost surface of the conductive drain electrode; and
wherein the dielectric structure continuously extends along a line between the bottommost surface of the conductive drain electrode to the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Hwu Jenn-Gwo
• Pan Samuel C
• Liao Chien-Shun

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D48/031

  of three-or-more electrode devices · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title