Method of forming graphene nanopattern by using mask formed from block copolymer

Patent metadata

Field	Value
Publication number	US-9748108-B2
Application number	US-201615068110-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Jul 7, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

First claim

What is claimed is:

1. A method of forming a graphene nanopattern, the method comprising:
providing a graphene layer on a substrate, the graphene layer having a smaller width than the substrate;
forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer,
the block copolymer layer including a plurality of first regions and a plurality of second regions arranged parallel to the graphene layer, and
one of the plurality of first regions being arranged along an edge portion of the graphene layer;
forming a mask pattern from the block copolymer layer by removing one of the plurality of first regions and the plurality of second regions of the block copolymer layer; and
patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask.

2. The method of claim 1 , wherein the forming the block copolymer layer includes forming the block copolymer layer to directly contact the graphene layer.

3. The method of claim 1 , wherein the forming the block copolymer layer includes forming the block copolymer layer to directly contact the region of the substrate that is exposed on the at least one side of the graphene layer.

4. The method of claim 1 , wherein the forming the block copolymer layer includes using a directed self-assembly (DSA) method assisted by the edge portion of the graphene layer without using a topological guide.

5. The method of claim 1 , wherein
the patterning the graphene layer includes forming a plurality of unit patterns, and
at least one of the plurality of unit patterns has a width that is greater than 0 nm and less than or equal to 10 nm.

6. The method of claim 5 , wherein the width of the at least one of the plurality of unit patterns is greater than 0 nm and less than or equal to 5 nm.

7. The method of claim 1 , wherein the graphene nanopattern includes a graphene nanoribbon (GNR).

8. The method of claim 1 , wherein
the edge portion of the graphene layer has a straight line shape, and
the graphene nanopattern includes a straight line pattern.

9. The method of claim 1 , wherein
the edge portion of the graphene layer has a curved line shape, and
the graphene nanopattern includes a curved line pattern.

10. The method of claim 1 , wherein the graphene layer has a width of several tens of nm to several hundreds of nm.

11. The method of claim 1 , wherein
the providing the graphene layer includes forming a plurality of graphene layers on the substrate, and
the forming the block copolymer layer includes forming the block copolymer layer on the plurality of graphene layers.

12. The method of claim 1 , wherein the substrate has a wafer scale.

13. The method of claim 1 , wherein
the substrate includes an insulation layer on a surface thereof, and
the forming the graphene layer includes forming the graphene layer on the insulation layer.

14. The method of claim 13 , wherein the insulation layer includes a hydrophilic material.

15. The method of claim 1 , wherein the block copolymer layer includes one of PS-b-PDMS, PS-b-P4VP, PS-b-P2VP, PS-b-PEO, PS-b-PAA, PS-b-PB, PS-b-PI, PI-b-P4VP, PI-b-P2VP, PI-b-PEO, PI-b-PAA, PMMA-b-P4VP, PMMA-b-P2VP, PMMA-b-PEO, PMMA-b-PAA, PS-b-PMA, PS-b-PMMA, PI-b-PMA, PI-b-PMMA, PMMA-b-PMA, PS-b-PS-OH, and PI-b-PS-OH.

16. The method of claim 1 , wherein
the forming the block copolymer layer includes,
forming a thin film by coating a surface of the graphene layer and the region of the substrate with a solution including a block copolymer, and
inducing a self-assembly of the block copolymer in the thin film by annealing the thin film.

17. A method of forming a graphene nanopattern, the method comprising:
providing a graphene layer on an underlayer;
forming a block copolymer layer directly on the graphene layer, the block copolymer layer including a plurality of first regions and a plurality of second regions alternately arranged in a direction parallel to the graphene layer, and one of the plurality of first regions being arranged along an edge portion of the graphene layer;
forming a mask pattern by removing one of the plurality of first regions and the plurality of second regions of the block copolymer layer; and
patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask.

18. The method of claim 17 , wherein the forming the block copolymer layer includes forming the block copolymer layer to directly contact a region of the underlayer that is exposed on at least one side of the graphene layer.

19. The method of claim 17 , wherein the forming the block copolymer layer includes using a directed self-assembly (DSA) method assisted by the edge portion of the graphene layer without using a topological guide.

20. A method of manufacturing a graphene-containing device, the method comprising:
forming a graphene nanopattern using the method of claim 1 ; and
forming a device unit including the graphene nanopattern.

21. The method of claim 20 , wherein the graphene-containing device includes one of a field effect transistor (FET), a tunneling device, a binary junction transistor (BJT), a barristor, a memory device, a solar cell, a photodetector, a sensor, and a light-emitting device.

22. The method of claim 20 , wherein
the graphene-containing device is a transistor, and
the graphene nanopattern is a channel layer of the transistor.

23. A method of forming a graphene nanopattern, the method comprising:
forming a block copolymer layer on a stack structure,
the stack structure including a graphene layer on a substrate,
the graphene layer having a width that is smaller than a width of the substrate such that the graphene layer exposes a region of the substrate along at least one side of the graphene layer,
the block copolymer layer including a plurality of first regions and a plurality of second regions alternately arranged on the graphene layer and the substrate,
one of the plurality of first regions being arranged along an edge portion of the graphene layer;
forming a mask pattern by removing one of the plurality of first regions and the plurality of second regions of the block copolymer layer; and
patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask.

24. The method of claim 23 , wherein
the block copolymer includes a first polymer and a second polymer,
the first polymer and the second polymer are different materials compared to each other,
the first polymer is hydrophobic compared to the second polymer,
the second eepolymer is hydrophilic compared to the first polymer,
the plurality of first regions are formed from the first polymer, and
the plurality of second regions are formed from the second polymer.

25. The method of claim 24 , wherein the block copolymer layer includes one of PS-b-PDMS, PS-b-P4VP, PS-b-P2VP, PS-b-PEO, PS-b-PAA, PS-b-PB, PS-b-PI, PI-b-P4VP, PI-b-P2VP, PI-b-PEO, PI-b-PAA, PMMA-b-P4VP, PMMA-b-P2VP, PMMA-b-PEO, PMMA-b-PAA, PS-b-PMA, PS-b-PMMA, PI-b-PMA, PI-b-PMMA, PMMA-b-PMA, PS-b-PS-OH, and PI-b-PS-OH.

26. The method of claim 24 , wherein
the forming the block copolymer on the stack structure includes forming the block copolymer directly on the graphene layer,
the patterning the graphene layer includes forming a plurality of unit patterns, and
at least one of the plurality of unit patterns has a width that is greater than 0 nm and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Seongjun
• Park Seongjun
• Lee Yunseong

Classifications

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/242

  of Group IV materials · CPC title