Semiconductor device and method of fabricating the same
US-9847422-B2 · Dec 19, 2017 · US
having the gate at least partly formed in a trench
having the gate at least partly formed in a trench · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D30/699 |
| Official title | {having the gate at least partly formed in a trench} |
| Display label | having the gate at least partly formed in a trench |
| Total patents | 201 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 21 |
| 2016 | 19 |
| 2017 | 23 |
| 2018 | 12 |
| 2019 | 15 |
| 2020 | 26 |
| 2021 | 22 |
| 2022 | 18 |
| 2023 | 21 |
| 2024 | 9 |
| 2025 | 13 |
| 2026 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method of forming a semiconductor device structure and semiconductor device structure
US-2017317097-A1 · Nov 2, 2017 · US
Erasable programmable non-volatile memory
US-2017301682-A1 · Oct 19, 2017 · US
Semiconductor apparatus with fake functionality
US-2017301634-A1 · Oct 19, 2017 · US
Random number generator device and control method thereof
US-2017301406-A1 · Oct 19, 2017 · US
Vertical memory devices and methods of manufacturing the same
US-9780096-B2 · Oct 3, 2017 · US
Semiconductor device and method of manufacturing semiconductor device
US-9754816-B2 · Sep 5, 2017 · US
Method of forming a semiconductor device structure and semiconductor device structure
US-9748259-B1 · Aug 29, 2017 · US
Inter-digitated capacitor in split-gate flash technology
US-2017213841-A1 · Jul 27, 2017 · US
Combined Gate and Source Trench Formation and Related Structure
US-2017200799-A1 · Jul 13, 2017 · US
Interdigitated capacitor in split-gate flash technology
US-9691780-B2 · Jun 27, 2017 · US
Method Of Manufacturing A Non-volatile Memory Cell And Array Having A Trapping Charge Layer In A Trench
US-2017148902-A1 · May 25, 2017 · US
Semiconductor device with buried gates and bit line contacting peripheral gate
US-9640626-B2 · May 2, 2017 · US
Semiconductor device and manufacturing method therefor
US-9640624-B2 · May 2, 2017 · US
Interdigitated capacitor in split-gate flash technology
US-2017092650-A1 · Mar 30, 2017 · US
Semiconductor device and method of fabricating the same
US-9595612-B2 · Mar 14, 2017 · US
Non-volatile memory and fabricating method thereof
US-9589977-B1 · Mar 7, 2017 · US
Semiconductor device and method of fabricating the same
US-2017033225-A1 · Feb 2, 2017 · US
Semiconductor devices including gate insulation layers on channel materials
US-9553105-B2 · Jan 24, 2017 · US
Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor
US-9548380-B2 · Jan 17, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D30/699?
- CPC H10D30/699 is the Cooperative Patent Classification code for “having the gate at least partly formed in a trench.”
- How many patents are filed under CPC H10D30/699 (having the gate at least partly formed in a trench)?
- Our database includes 201 publications tagged with this CPC code.
- Is patent activity under CPC H10D30/699 growing?
- Publication counts under this code: 9 in 2024 vs 13 in 2025 (latest complete years).