Combined Gate and Source Trench Formation and Related Structure

Patent metadata

Field	Value
Publication number	US-2017200799-A1
Application number	US-201614993292-A
Country	US
Kind code	A1
Filing date	Jan 12, 2016
Priority date	Jan 12, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.

First claim

1 . A semiconductor device comprising:
a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type; a gate trench in said semiconductor substrate and extending into said drift region to a first depth in said semiconductor substrate; a source trench in said semiconductor substrate and extending into said drift region, said source trench having a first portion and a second portion under said first portion, said first portion being wider than said gate trench, said second portion being narrower than said first portion, said first portion extending to said same first depth in said semiconductor substrate as said gate trench, said second portion extending to a second depth in said semiconductor substrate greater than said first depth; and a conductive filler in said source trench and insulated from the surrounding semiconductor substrate by a dielectric material, said dielectric material lining sidewalls of said first portion, sidewalls of said second portion and a bottom of said second portion.

2 . (canceled)

3 . The semiconductor device of claim 1 , further comprising a gate electrode and a gate trench dielectric liner in said gate trench.

4 . (canceled)

5 . The semiconductor device of claim 1 , wherein said source region is between said gate trench and said source trench.

6 . The semiconductor device of claim 1 , wherein said base region is between said gate trench and said source trench.

7 . The semiconductor device of claim 1 , further comprising a source contact coupled to said source region between said gate trench and said source trench.

8 . (canceled)

9 . The semiconductor device of claim 1 , wherein said semiconductor device comprises a MOSFET.

10 . The semiconductor device of claim 1 , wherein said semiconductor device comprises an IGBT.

11 . A method of forming a semiconductor device, said method comprising:
forming a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type; forming a gate trench and a first portion of a source trench in said semiconductor substrate and both extending into said drift region to a same first depth in said semiconductor substrate, said first portion of said source trench being wider than said gate trench; forming a gate electrode in said gate trench; after forming said gate trench and said first portion of said source trench, forming a second portion of said source trench under said first portion and extending deeper into said drift region than said first portion, said second portion being narrower than said first portion and extending to a second depth in said semiconductor substrate greater than said first depth; lining sidewalls of said first portion, sidewalls of said second portion and a bottom of said second portion with a dielectric material; and forming a conductive filler in said source trench, said conductive filler insulated from the surrounding semiconductor substrate by said dielectric material.

12 - 13 . (canceled)

14 . The method of claim 11 , further comprising forming a source contact coupled to said source region and said base region.

15 . The method of claim 14 , wherein said source contact is self-aligned between said source trench and said gate trench.

16 . The method of claim 11 , further comprising forming a gate trench dielectric liner in said gate trench.

17 . (canceled)

18 . The method of claim 11 , further comprising forming a patterned photoresist mask over said substrate to define a width of said first portion of said source trench and a width of said gate trench.

19 . The method of claim 11 , further comprising forming a contact trench between said source trench and said gate trench.

20 . (canceled)

21 . The semiconductor device of claim 1 , wherein said base region and said drift region are planar.

22 . The semiconductor device of claim 1 , wherein said drift region is formed in a Si epitaxial layer.

23 . The semiconductor device of claim 22 , wherein said base region comprises a first implanted region of said Si epitaxial layer.

24 . The semiconductor device of claim 23 , wherein said source region comprises a second implanted region of said Si epitaxial layer above said first implanted region.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Amali Adam
• Ma Ling

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H01L21/0273

  Electricity · mapped topic

• H01L29/7397

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic

• H01L29/66727

  Electricity · mapped topic