Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9754816-B2
Application number	US-201615087427-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Dec 15, 2008
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
preparing a semiconductor substrate;
forming a first insulating film over said semiconductor substrate;
after forming the first insulating film, forming first grooves in the first insulating film;
forming a gate electrode and a first interconnect in the first grooves, respectively;
forming a gate insulating film over the gate electrode;
forming a semiconductor layer over the gate insulating film;
forming a second insulating layer over the semiconductor layer and the first insulating film;
forming a via in the second insulating layer; and
forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via,
wherein the gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

2. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the first interconnects and the gate electrode are filled in the first insulating film by single damascene process or dual damascene process.

3. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the gate insulating film is formed by plasma CVD.

4. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the semiconductor layer is an oxide semiconductor layer; and
wherein the semiconductor layer is formed by sputtering and heated at a temperature of 400° C. or low.

5. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the semiconductor layer is a polysilicon layer or amorphous silicon; and
wherein the semiconductor layer is formed by plasma CVD.

6. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein a mask pattern as a mask is formed over the semiconductor layer to form a source-and-drain regions.

7. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the via is formed so as not to extend through the gate insulating film.

8. The method of manufacturing a semiconductor device as claimed in claim 1 ,
wherein the via falling outside the semiconductor is forming so as to extend through the gate insulating film.

9. A method of manufacturing a semiconductor device, comprising:
preparing a semiconductor substrate;
forming a first insulating film over the semiconductor substrate;
after forming the first insulating film, forming first grooves in the first insulating film;
forming a gate electrode and a first interconnect in the first grooves, respectively;
forming a gate insulating film over the gate electrode;
forming a semiconductor layer over the gate insulating film;
forming a second insulating layer over the semiconductor layer and the first insulating film;
forming a via in the second insulating layer; and
forming a second interconnect over the second insulating film such that the second interconnect is connected to the semiconductor layer through the via,
wherein the gate electrode and the first interconnect are formed by Cu or Cu alloy, respectively, and
wherein the second interconnect is formed by Al or Al alloy.

10. The method of manufacturing a semiconductor device as claimed in claim 9 ,
wherein the gate electrode and the first interconnect are filled in the first insulating film by single damascene process or dual damascene process.

11. The method of manufacturing a semiconductor device as claimed in claim 9 , wherein the gate insulating film is formed by plasma CVD.

12. The method of manufacturing a semiconductor device as claimed in claim 9 ,
wherein the semiconductor layer is an oxide semiconductor layer; and
wherein the semiconductor layer is formed by sputtering and heated at a temperature of 400° C. or low.

13. The method of manufacturing a semiconductor device as claimed in claim 9 ,
wherein the semiconductor layer is a polysilicon layer or amorphous silicon; and
wherein the semiconductor layer is formed by plasma CVD.

14. A method of manufacturing a semiconductor device, comprising:
forming a first insulating film over a semiconductor substrate;
after forming the first insulating film, forming first grooves in the first insulating film;
forming a gate electrode and a first interconnect in the first grooves, respectively;
forming a gate insulating film over the gate electrode;
forming a semiconductor layer over the gate insulating film;
forming a second insulating layer over the semiconductor layer and the first insulating film;
forming a via in the second insulating layer; and
forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via,
wherein the gate electrode and the first interconnect are formed by a first type alloy, respectively, and
wherein the second interconnect is formed by a second type alloy different than the first type alloy.

15. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein the first interconnects is filled in the first insulating film by a single damascene process or dual damascene process.

16. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein the gate electrode is filled in the first insulating film by single damascene process or dual damascene process.

17. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein the semiconductor layer is an oxide semiconductor layer; and
wherein the semiconductor layer is formed by sputtering and heated at a temperature of 400° C. or low.

18. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein the semiconductor layer is a polysilicon layer or amorphous silicon; and
wherein the semiconductor layer is formed by plasma CVD.

19. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein a mask pattern as a mask is formed over the semiconductor layer to form a source-and-drain regions.

20. The method of manufacturing a semiconductor device as claimed in claim 14 ,
wherein the via is formed so as not to extend through the gate insulating film, and
wherein the via falling outside the semiconductor is formed so as to extend through the gate insulating film.

Assignees

• Renesas Electronics Corp

Inventors

• Hayashi Yoshihiro
• Inoue Naoya
• Kaneko Kishou

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title

• H01L29/495

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic