Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9847422-B2
Application number	US-201615290269-A
Country	US
Kind code	B2
Filing date	Oct 11, 2016
Priority date	May 28, 2003
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor active region protruding upward from a semiconductor substrate, the semiconductor active region defined by and exposed above a surface of an isolation layer that is on the semiconductor substrate; and
rounding the semiconductor active region exposed above the surface of the isolation layer to form a first bend point in a sidewall of the semiconductor active region adjacent to the surface of the isolation layer and to form a second bend point in the sidewall of the semiconductor active region adjacent to a top surface of the semiconductor active region.

2. The method of claim 1 , wherein providing comprises:
forming at least one trench in the semiconductor substrate;
forming an isolation layer within the trench; and
performing a plurality of recessing processes on the isolation layer to expose edge portions of the semiconductor active region.

3. The method of claim 2 , wherein rounding comprises:
performing a plurality of rounding processes on the semiconductor active region exposed above the surface of the isolation layer to round the edge portions of the semiconductor active region.

4. The method of claim 3 , wherein each one of the plurality of rounding processes is followed by a respective one of the plurality of recessing processes repeatedly.

5. The method of claim 2 , wherein each of the plurality of recessing processes comprises one of wet etching or dry etching.

6. The method of claim 3 , wherein at least one of the plurality of rounding processes comprises etching the edge portions of the semiconductor active region.

7. The method of claim 6 , wherein the etching comprises isotropically etching or anisotropically etching the edge portions of the semiconductor active region.

8. The method of claim 7 , wherein the isotropic etching comprises one of wet etching or chemical dry etching.

9. The method of claim 7 , wherein the anisotropic etching comprises plasma dry etching.

10. The method of claim 3 , wherein the rounding comprises oxidizing the edge portions of the semiconductor active region.

11. The method of claim 10 , wherein the rounding further comprises:
removing an oxidized portion of the semiconductor active region.

12. The method of claim 2 , wherein a first one of the plurality of rounding processes comprises etching the edge portions of the semiconductor active region, and a second one of the plurality of rounding processes comprises oxidizing the edge portions of the semiconductor active region.

13. The method of claim 3 , wherein the recessing processes and the rounding processes are repeated until forming the edge portions to have a radius of curvature in a range from about ⅓ to about ½ of a width of an upper portion of the semiconductor active region.

14. The method of claim 1 , wherein the providing comprises forming the semiconductor active region and the semiconductor substrate from the same material.

15. The method of claim 1 , wherein providing further comprises providing the semiconductor active region to include first and second opposing sidewalls below the surface of the isolation layer; and
wherein rounding further comprises rounding the semiconductor active region exposed above the surface to form a rounded top surface of the semiconductor active region extending from the first opposing sidewall to the second opposing sidewall including no flat portion therebetween.

16. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor active region protruding upward from a semiconductor substrate, the semiconductor active region defined by and exposed above a surface of an isolation layer that is disposed on the semiconductor substrate; and
rounding the semiconductor active region exposed above the surface of the isolation layer to form a first bend point where a sidewall of the semiconductor active region transitions to an uppermost surface of the semiconductor active region and to form a second bend point in the sidewall of the semiconductor active region below the first bend point.

17. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor active region protruding upward from a semiconductor substrate, the semiconductor active region defined and exposed above a surface of an isolation layer disposed on the semiconductor substrate; and
rounding the semiconductor active region exposed above the surface of the isolation layer to form a first portion of a sidewall of the semiconductor active region below the surface of the isolation layer to have a first slope and to form a second portion of the sidewall of the semiconductor active region above the surface of the isolation layer to have a second slope that is different from the first slope.

18. A method comprising:
forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate;
after the forming the STI regions, oxidizing an upper portion of an active region between the STI regions, wherein a width of the upper portion of the active region is reduced by the oxidizing; and
recessing the STI regions, until a portion of the upper portion of the active region is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin.

19. The method of claim 18 , wherein in the oxidizing the upper portion of the active region, a lower portion of the active region is not oxidized.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jung-Hwan
• Leam Hun-Hyeoung
• Kim Tae-Hyun
• Nam Seok-Woo
• Namkoong Hyun
• Kim Yong-Seok
• Yu Tea-Kwang

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/0145 Primary

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title