Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9780096-B2
Application number	US-201514965532-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Jan 14, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

First claim

What is claimed is:

1. A vertical memory device comprising:
a substrate comprising a cell array region and a peripheral circuit region;
a cell gate stack structure in which a plurality of vertical channel structures are formed, the cell gate stack structure disposed in the cell array region and the plurality of vertical channel structures extending in a first direction perpendicular to a top surface of the substrate;
a first common source line contact plug passing through the cell gate stack structure between at least two of the vertical channel structures and extending in the first direction and in a second direction perpendicular to the first direction, the first common source line contact plug having an inner sidewall delimiting a recessed region; and
a buried film pattern disposed in the recessed region and comprising an insulating material.

2. The vertical memory device of claim 1 , further comprising:
a common source bit line, and
wherein the first common source line contact plug comprises a lower portion electrically connected to the substrate and an upper portion electrically connected to the common source bit line.

3. The vertical memory device of claim 2 ,
wherein the vertical memory device further comprises:
a common source bit line contact in contact with the inner sidewall of the first common source line contact plug, disposed on the buried film pattern, and electrically connected to the common source bit line.

4. The vertical memory device of claim 3 , wherein the common source bit line contact comprises a first portion disposed outside the recessed region and contacting a top surface of the first common source line contact plug and a second portion disposed inside the recessed region and contacting the inner sidewall of the first common source line contact plug and a top surface of the buried film pattern, and
wherein a width of the first portion is greater than a width of the second portion.

5. The vertical memory device of claim 1 , wherein the cell gate stack structure comprises a plurality of interlayer insulating film patterns spaced apart from each other along the first direction on the substrate and a plurality of cell gate lines disposed between the respective interlayer insulating film patterns and surrounding the plurality of vertical channel structures, and
wherein the vertical memory device further comprises a mold protection film contacting the cell gate stack structure in a portion of the cell array region and in the peripheral circuit region.

6. The vertical memory device of claim 5 , farther comprising:
a separation film pattern disposed between the plurality of cell gate lines and the first common source line contact plug and covering respective sidewalls of the plurality of cell gate lines.

7. The vertical memory device of claim 5 , further comprising:
a plurality of cell gate line contact plugs passing through the mold protection film and the plurality of interlayer insulating film patterns in the cell array region and connected to the respective cell gate lines; and
a peripheral circuit contact plug passing through the mold protection film in the peripheral circuit region and extending in the first direction, and
wherein respective top surfaces of the first common source line contact plug, the plurality of cell gate line contact plugs, and the peripheral circuit contact plugs are positioned on substantially a same plane.

8. The vertical memory device of claim 5 , further comprising:
an insulative capping film disposed on the cell gate stack structure and the mold protection film;
an upper insulating film disposed on the insulative capping film;
a plurality of cell gate line contact plugs passing through the upper insulating film, the insulative capping film, the mold protection film, and the plurality of interlayer insulating patterns in the cell array region and connected to the respective cell gate lines; and
a peripheral circuit contact plug passing through the upper insulating film, the insulative capping film, and the mold protection film in the peripheral circuit region and extending in the first direction, and
wherein the first common source line contact plug comprises a first part facing the plurality of cell gate lines and a second part facing the insulative capping film.

9. The vertical memory device of claim 8 , wherein a top surface of the first common source line contact plug is positioned on substantially a same plane as a top surface of the insulative capping film, and
wherein respective top surfaces of the plurality of cell gate line contact plugs and the peripheral circuit contact plug are positioned on substantially a same plane.

10. The vertical memory device of claim 8 , further comprising:
a cell bit line electrically connected to at least one of the plurality of vertical channel structures;
a common source bit line electrically connected to the first common source line contact plug; and
a connection wiring electrically connected to the peripheral circuit contact plug and at least one of the plurality of cell gate line contact plugs, and
wherein respective top surfaces of the cell bit line, the common source bit line, anti the connection wiring are positioned on substantially a same plane.

11. A vertical memory device comprising:
a substrate comprising a cell array region and a peripheral circuit region;
a cell gate stack structure in the cell array region;
a common source line contact plug passing through the cell gate stack structure and having an inner sidewall delimiting a recessed region;
a buried film pattern disposed in the recessed region and comprising an insulating material; and
a common source bit line contact electrically connected to the inner sidewall of the common source line contact plug.

12. A memory device comprising:
a plurality of vertical memory devices, each of which comprises a plurality of memory transistors connected in series and vertically stacked; and
a controller configured to control the vertical memory devices, and
wherein each of the vertical memory devices comprises:
a substrate comprising a cell array region and a peripheral circuit region;
a cell gate stack structure disposed in the cell array region and in which an opening for a common source line is formed to extend in a first direction perpendicular to a top surface of the substrate and in a second direction perpendicular to the first direction;
a first common source line contact plug formed in the opening for the common source line and having an inner sidewall delimiting a recessed region in the opening for the common source line; and
a buried film pattern disposed in the recessed region and comprising art insulating material.

Assignees

• Park Sang-Yong
• Rho Kee-Jeong
• Park Hyeong
• Lim Tae-Wan
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Yong
• Rho Kee-Jeong
• Park Hyeong
• Lim Tae-Wan

Classifications

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W74/137 Primary

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L27/10897 Primary

  Electricity · mapped topic