Method Of Manufacturing A Non-volatile Memory Cell And Array Having A Trapping Charge Layer In A Trench

Patent metadata

Field	Value
Publication number	US-2017148902-A1
Application number	US-201615368451-A
Country	US
Kind code	A1
Filing date	Dec 2, 2016
Priority date	Mar 14, 2013
Publication date	May 25, 2017
Grant date	—

Abstract

A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

First claim

1 . A method of forming a non-volatile memory cell, comprising:
forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type; forming first and second spaced apart regions of a second conductivity type in the substrate with the first region formed under the trench with a channel region between the first region and the second region, wherein a first portion of the channel region is along a sidewall of the trench and a second portion of the channel region is along the surface of the substrate; forming a charge trapping layer in said trench adjacent to and insulated from the first portion of the channel region, for controlling the conduction of the first portion of the channel region; forming a coupling gate in the trench adjacent to and insulated from the charge trapping layer, and insulated from the first region; and forming a control gate insulated from the second portion of the channel region only by a single insulation layer, without any conductive gate disposed between the control gate and the second portion of the channel region; wherein said charge trapping layer is in the trench and extends no higher than the single insulation layer, and wherein said conductive gate is in said trench and extends no higher than the single insulation layer.

2 . The method of claim 1 wherein said charge trapping layer is silicon nitride.

3 . The method of claim 1 wherein said control gate is only above the surface.

4 . A method of forming an array of non-volatile memory cells in a substrate material having a first conductivity type and a surface; said method comprising:
forming a plurality of spaced apart trenches, substantially parallel to one another extending in a row direction, in the surface of the substrate; forming a plurality of first regions, with each first region formed under each trench extending in the row direction with each first region being of a second conductivity type; forming a plurality of second regions along the surface of the substrate between trenches, in a column direction substantially perpendicular to the row direction, with a channel region for each memory cell between each second region and an adjacent first region; said channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate, adjacent to the second region; forming a pair of charge trapping layers in the trench in each column, each charge trapping layer adjacent to and insulated from the sidewalls of the trench along the first portion of the channel region for controlling the conduction of the first portion of the channel region; forming a plurality of electrically conductive gates, with a conductive gate in each trench extending in the row direction, adjacent to and insulated from the charge trapping layers of each column and from the first region and capacitively coupled to the charge trapping layers; and forming a plurality of spaced apart electrically conductive control gates, parallel to one another, extending in the row direction, disposed over and insulated from the second portion of each channel region only by a single insulation layer, without any conductive gate disposed between the control gates and the second portion of each channel region, for controlling the conduction of each second portion of the channel region; wherein said charge trapping layer is in the trench and extends no higher than the single insulation layer, and wherein said conductive gate is in said trench and extends no higher than the single insulation layer.

5 . The method of claim 4 wherein said charge trapping layer is silicon nitride.

6 . The method of claim 4 wherein said control gate is only above the surface.

Assignees

• Silicon Storage Tech Inc

Inventors

• Do Nhan

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H01L27/11568

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L29/42352

  Electricity · mapped topic

• H01L21/0217

  Electricity · mapped topic