Integrated memory, integrated assemblies, and methods of forming memory arrays

Patent metadata

Field	Value
Publication number	US-10475697-B2
Application number	US-201815982949-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	Jan 6, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.

First claim

I claim:

1. An integrated assembly, comprising:
a first memory array deck comprising a plurality of first memory cells having first capacitors containing only non-ferroelectric insulative material;
a second memory array deck comprising a plurality of second memory cells having second capacitors containing ferroelectric insulative material; and
a base supporting the first and second memory array decks, the first and second memory array decks being disposed at different elevations over the base relative to each other.

2. The integrated assembly of claim 1 , wherein the first memory array deck is over the second memory array deck.

3. The integrated assembly of claim 1 , wherein the second memory array deck is over the first memory array deck.

4. The integrated assembly of claim 1 , wherein the first capacitors are spaced from one another by void regions.

5. The integrated assembly of claim 1 , wherein the second capacitors are spaced from one another by void regions.

6. The integrated assembly of claim 1 , wherein the first capacitors are spaced from one another by void regions of the first memory array deck, and wherein the second capacitors are spaced from one another by void regions of the second memory array deck.

7. The integrated assembly of claim 1 , wherein:
the first memory cells comprise first transistors electrically coupled with the first capacitors in an arrangement XTYC; where X and Y are integers, where T is transistor and C is capacitor; and
the second memory cells comprise second transistors electrically coupled with the second capacitors in the arrangement XTYC.

8. The integrated assembly of claim 7 , wherein the arrangement XTYC is 1T1C.

9. The integrated assembly of claim 1 , wherein:
the first memory cells comprise first transistors electrically coupled with the first capacitors in a first arrangement XTYC; where X and Y are integers, T is transistor and C is capacitor;
the second memory cells comprise second transistors electrically coupled with the second capacitors in a second arrangement PTQC; where P and Q are integers, T is transistor and C is capacitor; and
wherein the second arrangement comprises a different number of transistors and/or capacitors as compared to the first memory cell arrangement.

10. The integrated assembly of claim 9 , wherein the first arrangement XTYC is 1T1C.

11. The integrated assembly of claim 9 , wherein the second arrangement PTQC is 1T1C.

12. An integrated assembly, comprising:
a first memory array deck having a plurality of first transistors electrically coupled the first capacitors in a first arrangement XTYC; where X and Y are integers, T is transistor and C is capacitor;
a second memory array deck having a plurality of second transistors electrically coupled with the second capacitors in a second arrangement PTQC; where P and Q are integers, T is transistor and C is capacitor; where P is different from X and/or Q is different from Y; and
a base supporting the first and second memory array decks, the first and second memory array decks being disposed at different elevations over the base relative to each other.

13. The integrated assembly of claim 12 , wherein the first arrangement XTYC is 1T1C.

14. The integrated assembly of claim 12 , wherein the second arrangement PTQC is 1T1C.

15. The integrated assembly of claim 12 , wherein the first capacitors comprise ferroelectric insulative material and/or the second capacitors comprise ferroelectric insulative material.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20 Primary

  Air gaps · CPC title

• H01L28/90

  Electricity · mapped topic

• H01L27/10808

  Electricity · mapped topic

• H01L27/11504

  Electricity · mapped topic