Three-dimensional ferroelectric NOR-type memory

Patent metadata

Field	Value
Publication number	US-10651182-B2
Application number	US-201816146663-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.

First claim

What is claimed is:

1. A system comprising:
a substrate;
first, second, and third word lines;
first, second, and third layers, wherein the first layer is between the substrate and the first word line, the second layer is between the first and second word lines, and the third layer is between the second and third word lines;
first, second, and third portions of a material, wherein the first portion of the material is between the first word line and the first layer, the second portion of the material is between the second word line and the second layer, and the third portion of the material is between the third word line and the third layer;
a monolithic semiconductor layer on the first, second, and third portions of the material;
a bit line having a long axis and a short axis;
wherein the first layer includes a metal, the second layer includes the metal, and the third layer includes the metal;
wherein the material includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof;
wherein (a) a first plane, parallel to the short axis, intersects the first layer, the semiconductor layer, and the bit line; (b) a second plane, parallel to the short axis, intersects the second layer, the semiconductor layer, and the bit line; and (c) a third plane, parallel to the short axis, intersects the third layer, the semiconductor layer, and the bit line.

2. The system of claim 1 comprising a NOR logic gate, wherein:
the NOR logic gate includes the first, second, and third portions of the material; and
the NOR logic gate includes the semiconductor layer.

3. The system of claim 2 comprising:
a first axis that is parallel to the long axis, the first axis intersecting the first, second, and third word lines and the first, second, and third portions of the material;
a second axis that is parallel to the long axis, the second axis intersecting the first, second, and third layers;
wherein the first axis does not intersect any of the first, second, or third layers.

4. The system of claim 3 wherein the second axis intersects the first, second, and third word lines and the first, second, and third portions of the material.

5. The system of claim 4 wherein the first axis intersects the semiconductor layer.

6. The system of claim 4 comprising a switching device, wherein:
the switching device includes a source, a channel, and a drain;
the source includes the semiconductor layer;
the channel includes the semiconductor layer;
the drain includes the semiconductor layer;
the system comprises:
a gate corresponding to the channel, the gate including a portion of the first word line;
a source contact corresponding to the source, the source contact including a portion of the first layer;
a drain contact corresponding to the drain, the drain contact including a portion of the bit line.

7. The system of claim 6 comprising an additional switching device, wherein:
the additional switching device includes an additional source, an additional channel, and an additional drain;
the additional source includes the semiconductor layer;
the additional channel includes the semiconductor layer;
the additional drain includes the semiconductor layer;
the system comprises:
an additional gate corresponding to the additional channel, the additional gate including a portion of the second word line;
an additional source contact corresponding to the additional source, the additional source contact including a portion of the second layer;
an additional drain contact corresponding to the additional drain, the additional drain contact including an additional portion of the bit line;

wherein the first axis intersects the switching device and the additional switching device;
wherein the switching device and the additional switching device are coupled to the bit line in parallel with each other.

8. The system of claim 6 comprising first and second memory cells, wherein:
the first memory cell includes the switching device;
the second memory cell does not include the switching device;
the first and second memory cells are included in random access memory (RAM);
the first memory cell is addressable independently of the second memory cell.

9. The system of claim 6 comprising:
a first insulator material between the first layer and the first portion of the material, the first insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof;
a second insulator material between the second layer and the second portion of the material, the second insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof; and
a third insulator material between the third layer and the third portion of the material, the third insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof;
the second axis intersects the first, second, and third insulator materials.

10. The system of claim 9 comprising a third axis, parallel to the long axis, wherein:
the third axis intersects: (a) the first, second, and third word lines, (b) the first, second, and third portions of the materials, and (c) the first, second, and third insulator materials;
the third axis does not intersect any of the first, second, or third layers.

11. The system of claim 10 wherein the third axis intersects the semiconductor layer.

12. The system of claim 11 comprising:
an additional first insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof, the additional first insulator material: (a)(i) being between the first word line and the substrate, and (a)(ii) being between the semiconductor layer and the bit line;
an additional second insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof, the additional second insulator material: (a)(i) being between the first and second word lines, and (a)(ii) being between the semiconductor layer and the bit line;
an additional third insulator material including at least one of oxygen, nitrogen, carbon, or combinations thereof, the additional third insulator material: (a)(i) being between the second and third word lines, and (a)(ii) being between the semiconductor layer and the bit line.

13. The system of claim 2 comprising:
an integrated circuit on a first die;
a memory on a second die, the memory comprising the NOR logic gate; and
the first and second die on a package substrate.

14. The system of claim 13 wherein the integrated circuit comprises a field programmable gate array (FPGA).

15. The system of claim 13 comprising:
a radiofrequency receiver; and
a chassis;
wherein the chassis includes the radiofrequency receiver and the package substrate.

16. The system of claim 2 comprising:
a processor;
a processor memory cache corresponding to the processor;
wherein the processor memory cache includes the NOR logic gate.

17. The system of claim 2 comprising random access memory (RAM) that includes the NOR logic gate.

18. The system of claim 2 wherein the semiconductor layer includes a continuous portion of the semiconductor layer that extends, uninterrupted, from the first layer to the third word line.

19. The system of claim 2 wherein:
the metal includes at least one of tungsten, copper, aluminum, tantalum, titanium, cobalt, or combinations thereof;
the first word line includes an additional metal;
the second word line includes the additional metal;
the third word line includes the additio

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title