Cell disturb prevention using a leaker device to reduce excess charge from an electronic device

Patent metadata

Field	Value
Publication number	US-10777563-B2
Application number	US-201816228072-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Nov 1, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
multiple electronic devices each having a bottom electrode that is at least partially electrically isolated from the bottom electrodes of the other electronic devices of the multiple electronic devices; and
a resistive interconnect electrically coupled to two or more of the bottom electrodes, the resistive interconnect being configured to discharge at least a portion of excess charge from the two or more bottom electrodes and including an interconnect line directly coupled to each of the two or more bottom electrodes.

2. The apparatus of claim 1 , wherein the resistive interconnect is electrically coupled to an uppermost portion of the bottom electrode of the two or more of the multiple electronic devices.

3. The apparatus of claim 1 , wherein the resistive interconnect is electrically coupled to a lowermost portion of the bottom electrode of the two or more of the multiple electronic devices.

4. The apparatus of claim 1 , wherein the resistive interconnect is electrically coupled to a portion of the bottom electrode of the two or more of the multiple electronic devices located between an uppermost portion and a lowermost portion of the bottom electrode.

5. The apparatus of claim 1 , wherein at least some of the multiple electronic devices comprise a ferroelectric material.

6. The apparatus of claim 5 , wherein the ferroelectric material comprises lead zirconate titanate (PZT).

7. The apparatus of claim 1 , wherein the multiple electronic devices comprise a memory array.

8. The apparatus of claim 1 , further comprising a substrate, and wherein the multiple electronic devices are formed upon the substrate, and the interconnect line is directly coupled to the substrate.

9. The apparatus of claim 1 , wherein the resistive interconnect comprises a plurality of interconnect lines including the interconnect line directly coupled to each of the two or more bottom electrodes.

10. The apparatus of claim 1 , wherein the resistive interconnect comprises a single layer of material.

11. The apparatus of claim 1 , wherein the resistive interconnect comprises multiple levels of material, each layer of the multiple levels being separated from one another by a respective dielectric level.

12. A method comprising:
forming multiple electronic devices, each device of the multiple electronic devices having at least one electrode; and
forming a leaker device to electrically couple two or more electrodes of at least a portion of the multiple electronic devices to each other using an interconnect line directly coupled to each of the two or more electrodes. the leaker device to drain at least a portion of excess charge from the two or more electrodes.

13. The method of claim 12 , further comprising selecting a resistance of the leaker device to discharge at least a portion of excess charge from the two or more electrodes while not electrically shorting the two or more electrodes to one another.

14. The method of claim 13 , further comprising selecting the resistance of the leaker device to be within a range from about 0.1 MΩ to about 5 MΩ.

15. The method of claim 12 , further comprising forming a contact line between the leaker device and a substrate upon which the multiple electronic devices are formed, wherein the contact line is coupled on a first end to the leaker device and on a second end to the substrate.

16. The method of claim 12 , further comprising forming a contact line between the leaker device and a discharge structure, wherein the contact line is coupled on a first end to the leaker device and on a second end to the discharge structure.

17. The method of either claim 15 or claim 16 , wherein the contact line comprises at least one conductive material selected from conductive materials including metals, transition metals, metal-containing compositions, conductively-doped semiconductor materials, and an oxynitride of the metals or the transition metals.

18. An apparatus, comprising:
multiple memory cells disposed in rows and columns, each memory cell of the multiple memory cells having a bottom electrode at least partially electrically isolated from the bottom electrodes of other memory cells of the multiple memory cells;
multiple leaker devices each comprising a resistive interconnect, wherein one of the multiple leaker devices includes an interconnect line directly coupled to each of the bottom electrodes within a respective row of the multiple memory devices, each leaker device being configured to discharge at least a portion of excess charge from the bottom electrodes coupled to that leaker device to prevent a memory cell disturb while not electrically shorting the bottom electrodes coupled to that leaker device to one another; and
a contact line electrically coupling each of the multiple leaker devices to a discharge structure.

19. The apparatus of claim 18 , wherein the multiple leaker devices each comprise at least one material selected from materials including amorphous silicon, niobium monoxide, and silicon nitride.

20. The apparatus of claim 18 , wherein each of the multiple memory cells is coupled to each other within a given row and across adjacent rows by at least one of the leaker devices.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal

Classifications

• H10D86/85

  characterised by only passive components · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2295

  Protection circuits or methods · CPC title