Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10347627-B2
Application number	US-201815926572-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Jun 14, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of active patterns extending in a first direction;
a plurality of gate structures crossing the active patterns and extending in a second direction crossing the first direction;
a device isolation layer extending in the second direction between adjacent first and second ones of the plurality of gate structures;
a plurality of contact patterns between the plurality of gate structures and the device isolation layer;
a plurality of connection patterns connected to the plurality of contact patterns, respectively, wherein the device isolation layer is between the plurality of connection patterns, and wherein the plurality of connection patterns are spaced apart from each other by a first distance in the first direction; and
a plurality of wiring patterns connected to the plurality of connection patterns, respectively, wherein the device isolation layer is between the plurality of wiring patterns, and wherein the plurality of wiring patterns are spaced apart from each other in the first direction by a second distance that is longer than the first distance.

2. The semiconductor device of claim 1 ,
wherein the device isolation layer comprises a width that is shorter than the first distance, and
wherein the device isolation layer is at a boundary between a first cell comprising a first N-well region and a first P-well region and a second cell comprising a second N-well region and a second P-well region.

3. The semiconductor device of claim 1 , wherein the device isolation layer comprises a width that is shorter than twice a width of one of the plurality of gate structures.

4. The semiconductor device of claim 1 ,
wherein the device isolation layer is in one of the plurality of active patterns, and
wherein the device isolation layer comprises a bottom surface that is lower than a top surface of the one of the plurality of active patterns and a top surface that is higher than the top surface of the one of the plurality of active patterns.

5. The semiconductor device of claim 1 , wherein the plurality of connection patterns extend in the first direction and overlap at least a portion of the plurality of gate structures, respectively.

6. The semiconductor device of claim 1 , wherein the plurality of wiring patterns extend in the first direction and contact the plurality of connection patterns, respectively.

7. The semiconductor device of claim 1 , wherein one of the plurality of wiring patterns overlaps one of the plurality of contact patterns.

8. The semiconductor device of claim 1 ,
wherein the plurality of contact patterns comprises a first metallic material, and
wherein the plurality of connection patterns comprises a second metallic material comprising a resistivity that is lower than a resistivity of the first metallic material.

9. The semiconductor device of claim 8 ,
wherein the plurality of wiring patterns comprise the second metallic material, and
wherein the semiconductor device further comprises an interface between the plurality of wiring patterns and the plurality of connection patterns.

10. A semiconductor device comprising:
a plurality of active patterns extending in a first direction;
a device isolation layer crossing the plurality of active patterns and extending in a second direction crossing the first direction;
a gate structure spaced apart from the device isolation layer and extending in the second direction to cross the plurality of active patterns;
a plurality of source/drain impurity layers adjacent opposite sides of the gate structure;
a contact pattern connected to one of the plurality of source/drain impurity layers that is between the device isolation layer and the gate structure;
a connection pattern connected to the contact pattern and spaced apart by a first distance in the first direction from an axis that is aligned with the device isolation layer; and
a wiring pattern connected to the connection pattern and spaced apart in the first direction from the axis that is aligned with the device isolation layer by a second distance that is longer than the first distance.

11. The semiconductor device of claim 10 ,
wherein the device isolation layer comprises a width in the first direction that is shorter than a distance in the first direction between the device isolation layer and the gate structure, and
wherein the gate structure is adjacent the device isolation layer.

12. The semiconductor device of claim 10 , wherein:
the connection pattern extends in the first direction and overlaps the gate structure;
the device isolation layer is at a boundary between a first cell comprising a first N-well region and a first P-well region and a second cell comprising a second N-well region and a second P-well region;
the connection pattern comprises a first connection pattern in the first cell;
the semiconductor device further comprises a second connection pattern in the second cell;
the axis comprises a first axis that is aligned with a first side of the device isolation layer; and
the second connection pattern is spaced apart by the first distance in the first direction from a second axis that is parallel to the first axis and that is aligned with a second side of the device isolation layer.

13. The semiconductor device of claim 10 ,
wherein the wiring pattern contacts a portion of the connection pattern, and
wherein the connection pattern is adjacent a boundary between first and second cells of the semiconductor device.

14. The semiconductor device of claim 10 ,
wherein the contact pattern comprises a first metallic material, and
wherein the connection pattern and the wiring pattern comprise a second metallic material different from the first metallic material.

15. A semiconductor device comprising:
a substrate comprising a first cell region comprising a first N-well region and a first P-well region and a second cell region comprising a second N-well region and a second P-well region;
a gate structure on the first cell region of the substrate;
first and second source/drain impurity regions on the substrate adjacent opposite first and second sides, respectively, of the gate structure;
a third source/drain impurity region on the second cell region of the substrate;
a first contact connected to the first source/drain impurity region and comprising a first metallic material;
a first connector that is connected to the first contact and extends to overlap at least a portion of the gate structure,
wherein the first connector comprises a second metallic material different from the first metallic material;
a second contact connected to the third source/drain impurity region; and
a second connector that is connected to the second contact.

16. The semiconductor device of claim 15 , further comprising a device isolation region in the substrate,
wherein the first contact is between the device isolation region and the gate structure, and
wherein the device isolation region is at a boundary between the first cell region and the second cell region.

17. The semiconductor device of claim 15 ,
wherein the semiconductor device further comprises a third contact that is connected to the second source/drain impurity region, and
wherein the first connector connects the first contact and the third contact to each other.

18. The semiconductor device of claim 15 , further comprising:
a first wiring pattern connected to the first connector and comprising the second metallic material; and
a second wiring pattern connected to the second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Moon Gi
• Kim Hyeonuk
• Shin Jongchan
• Hwang Eryung
• Yang Jaeseok
• Jeong Jinwoo

Classifications

• H10W20/4424

  Copper alloys · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11587

  Electricity · mapped topic