Semiconductor device having ferroelectric layer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10490571-B2
Application number	US-201815975721-A
Country	US
Kind code	B2
Filing date	May 9, 2018
Priority date	May 31, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure, including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked, on a substrate;
forming a trench passing through the stacked structure on the substrate;
forming a crystalline liner insulating layer on a sidewall surface of the trench;
forming a ferroelectric insulating layer and a channel layer on the crystalline liner insulating layer;
selectively removing the interlayer sacrificial layers and the crystalline liner insulating layer to form a recess selectively exposing the ferroelectric insulating layer; and
forming an electrode layer by filling the recess with a conductive layer.

2. The method of claim 1 , wherein the interlayer insulating layer and the interlayer sacrificial layer have etching selectivity with each other.

3. The method of claim 1 , wherein a lattice constant of the crystalline insulating layer is different from a lattice constant of the ferroelectric insulating layer.

4. The method of claim 1 , wherein forming the crystalline liner insulating layer comprises:
forming an amorphous metal oxide layer along an inner wall of the trench; and
crystallizing the metal oxide layer by heat treatment.

5. The method of claim 4 , wherein the metal oxide layer comprises at least one selected from the group consisting of magnesium oxide, calcium oxide, strontium oxide, barium oxide, aluminum oxide, gallium oxide, yttrium oxide, scandium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, lanthanum oxide, gadolinium oxide, zirconium silicon oxide, hafnium silicon oxide, and titanium silicon oxide.

6. The method of claim 1 , wherein forming the ferroelectric insulating layer and the channel layer comprises:
forming an amorphous ferroelectric material layer on the crystalline liner insulating layer;
forming a semiconductor material layer on the ferroelectric material layer; and
crystallizing the ferroelectric material layer by heat treatment using the crystalline liner insulating layer as a capping layer.

7. The method of claim 6 , further comprising forming an interfacial insulating layer on the ferroelectric material layer after forming the ferroelectric material layer and forming the semiconductor material layer on the interfacial insulating layer,
wherein the interfacial insulating layer comprises silicon oxide or aluminum oxide.

8. The method of claim 1 , wherein the ferroelectric insulating layer comprises at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

9. The method of claim 8 , wherein the ferroelectric insulating layer comprises at least one selected from the group consisting of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), and gadolinium (Gd).

10. The method of claim 1 , wherein forming the recess comprises:
selectively removing the interlayer sacrificial layers by wet etching to expose a sidewall of the crystalline liner insulating layer; and
wet-etching the sidewall of the exposed crystalline liner insulating layer to expose the ferroelectric insulating layer.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Hyangkeun
• Kim Joong Sik

Classifications

• H01L29/517

  Electricity · mapped topic

• H01L27/11597 Primary

  Electricity · mapped topic

• H01L29/78391

  Electricity · mapped topic

• H01L27/11507

  Electricity · mapped topic

• H01L29/6684

  Electricity · mapped topic