Semiconductor device

Patent metadata

Field	Value
Publication number	US-9865617-B2
Application number	US-201715402272-A
Country	US
Kind code	B2
Filing date	Jan 10, 2017
Priority date	May 12, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first interlayer insulating layer and a second interlayer insulating layer;
a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer; and
vertical structures each extending vertically through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern,
wherein each of the first interlayer insulating layer and the second interlayer insulating layer has a first side surface and a second side surface facing in opposite directions with respect to each other, first regions disposed adjacent to the first side surface and the second side surface thereof, respectively, and a second region interposed between the first regions, and
in each of the first interlayer insulating layer and the second interlayer insulating layer the first regions have an impurity concentration different from that of the second region such that in each of the first insulating layer and the second interlayer insulating layer the impurity concentration of is non-uniform along an axis parallel to the opposite directions.

2. The semiconductor device of claim 1 , wherein in each of the first interlayer insulating layer and the second interlayer insulating layer, a portion of the second region has an impurity concentration lower than the impurity concentration of the first regions.

3. The semiconductor device of claim 1 , wherein in each of the first interlayer insulating layer and the second interlayer insulating layer, a portion of the second region is thicker than the first regions.

4. The semiconductor device of claim 1 , wherein the vertical structures comprise external vertical structures disposed adjacent to the first side surfaces and the second side surfaces of the first interlayer insulating layer and the second interlayer insulating layer, and internal vertical structures disposed further from the first side surfaces and the second side surfaces of the first interlayer insulating layer and the second interlayer insulating layer than the external vertical structures.

5. The semiconductor device of claim 4 , wherein impurity concentrations of portions of the first interlayer insulating layer and the second interlayer insulating layer disposed adjacent to the internal vertical structures are lower than impurity concentrations of portions of the first interlayer insulating layer and the second interlayer insulating layer disposed adjacent to the first side surfaces and the second side surfaces of the first interlayer insulating layer and the second interlayer insulating layer.

6. The semiconductor device of claim 1 , wherein the vertical structures comprise a first group of vertical channel structures disposed adjacent to the first side surface of each of the first and second interlayer insulating layers, a second group of vertical channel structures disposed adjacent to the second side surface of each of the first and second interlayer insulating layers, and vertical dummy structures disposed between the first and second groups of vertical channel structures,
wherein the impurity concentrations of portions of the first interlayer insulating layer and the second interlayer insulating layer disposed adjacent to the vertical dummy structures are lower than the impurity concentration of portions of the first interlayer insulating layer and the second interlayer insulating layer disposed adjacent to the first side surface and the second side surface of each of the first interlayer insulating layer and the second interlayer insulating layer.

7. The semiconductor device of claim 1 , further comprising a semiconductor substrate,
wherein the first interlayer insulating layer, the second interlayer insulating layer, the horizontal conductive pattern, and the vertical structures are disposed on the semiconductor substrate.

8. The semiconductor device of claim 7 , further comprising a gate dielectric structure disposed between the vertical structures and the horizontal conductive pattern,
wherein the gate dielectric structure comprises a data storage layer.

9. The semiconductor device of claim 8 , wherein the gate dielectric structure comprises a first dielectric structure and a second dielectric structure, the first dielectric structure has one portion interposed between the horizontal conductive pattern and the vertical structures and another portion extending between the first interlayer insulating layer and each of the vertical structures and between the second interlayer insulating layer and each of the vertical structures,
the second dielectric structure has one portion interposed between the first dielectric structure and the horizontal conductive pattern and another portion extending between the first interlayer insulating layer and the horizontal conductive pattern and between the second interlayer insulating layer and the horizontal conductive pattern, and
one of the first dielectric structure and the second dielectric structure comprises the data storage layer.

10. A semiconductor device, comprising:
interlayer insulating layers and horizontal conductive patterns alternately stacked on a substrate, each of the interlayer insulating layers having a first side surface and a second side surface facing in opposite directions with respect to each other;
vertical structures extending through the interlayer insulating layers and the horizontal conductive patterns; and
data storage layers disposed between the vertical structures and the horizontal conductive patterns,
wherein each of the interlayer insulating layers has first regions disposed adjacent to the first side surface and the second side surface thereof, respectively, and a second region interposed between the first regions, a portion of the second region is thicker than the first regions, and the first regions have an impurity concentration higher than that of the portion of the second region that is thicker than the first regions such that in each of the interlayer insulating layers the impurity concentration is non-uniform along an axis parallel to the opposite directions.

11. The semiconductor device of claim 10 , wherein comparative etching rates of the first regions with the second region are such that the etching rate of the first regions is different from the etching rate of the portion of the second region that is thicker than the first regions.

12. The semiconductor device of claim 10 , further comprising separation patterns disposed on the substrate as laterally spaced apart from each other,
wherein the interlayer insulating layers and the horizontal conductive patterns are interposed between the separation patterns.

13. The semiconductor device of claim 12 , further comprising insulating spacers on side surfaces of the separation patterns,
wherein the insulating spacers have portions disposed between the separation patterns and the horizontal conductive patterns and extend from said portions between the separation patterns and the interlayer insulating layers.

14. The semiconductor device of claim 10 , wherein the data storage layers are charge trap layers.

15. A semiconductor device, comprising:
a substrate;
separation structures disposed on the substrate and comprising insulating material;
a stack of horizontal layers disposed on the substrate and interposed between the insulating material of the separation structure, the horizontal layers including interlayer insulating layers and conductive lines alternately disposed in a vertical direction in the stack such that each of the conduc

Assignees

• Han Hauk
• Im Ji Woon
• Kim Do Hyung
• Lim Hyun Seok
• Samsung Electronics Co Ltd

Inventors

• Han Hauk
• Im Ji Woon
• Kim Do Hyung
• Lim Hyun Seok

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/0649

  Electricity · mapped topic