Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9876028-B2
Application number	US-201615266158-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Jan 11, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

The memory string comprises: a plurality of control gate electrodes stacked on the substrate and extending in a first direction and a second direction parallel to the substrate; a semiconductor layer that has one end thereof connected to the substrate, has as its longitudinal direction a third direction perpendicular to the substrate, and faces the plurality of control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the semiconductor layer. The contact includes, in the third direction, a first portion, a second portion which is more to a substrate side than is the first portion, and a third portion which is more to the substrate side than is the second portion. A width of the second portion is larger than a width of the first portion, and larger than a width of the third portion.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising a memory string that comprises a plurality of memory cells connected in series, and the semiconductor memory device comprising a contact electrically connected to one end of the memory string, the method comprising:
forming a memory string that penetrates a stacked body, the stacked body including, stacked on a substrate, a plurality of control gate electrodes and an inter-layer insulating layer positioned between the plurality of control gate electrodes;
depositing a first insulating layer on the stacked body;
forming a first opening that penetrates the first insulating layer and the stacked body;
depositing a second insulating layer on the first insulating layer, such that the first opening is not blocked and such that in an upper portion of the first opening, a width of a second portion is larger than a width of a first portion positioned more upwardly than is the second portion; and
the first opening is implanted with a conductive layer to form the contact.

2. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the conductive layer is implanted such that a void is formed on the inside of the first opening.

3. The method of manufacturing a semiconductor memory device according to claim 2 , wherein
the conductive layer is implanted such that an upper end of the void exists more to an upper side than does an upper end of the memory string.

4. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the conductive layer is tungsten (W).

5. The method of manufacturing a semiconductor memory device according to claim 1 , wherein
the first opening has a plate-like shape extending in a third direction perpendicular to the substrate and a first direction along the substrate.

6. The method of manufacturing a semiconductor memory device according to claim 1 , further comprising
after implanting the conductive layer, removing the first insulating layer and the second insulating layer by executing a CMP method.

7. The method of manufacturing a semiconductor memory device according to claim 6 , wherein
the conductive layer is implanted such that a void is formed on the inside of the first opening.

8. The method of manufacturing a semiconductor memory device according to claim 7 , wherein
the conductive layer is implanted such that an upper end of the void exists more to an upper side than does an upper end of the memory string.

9. The method of manufacturing a semiconductor memory device according to claim 6 , wherein
the conductive layer is tungsten (W).

10. The method of manufacturing a semiconductor memory device according to claim 6 , wherein
the first opening has a plate-like shape extending in a third direction perpendicular to the substrate and a first direction along the substrate.

Assignees

• Toshiba Memory Corp

Inventors

• Konagai Satoshi

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L27/11563

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11553

  Electricity · mapped topic