Semiconductor device including interlayer support patterns on a substrate

Patent metadata

Field	Value
Publication number	US-10115734-B2
Application number	US-201715398735-A
Country	US
Kind code	B2
Filing date	Jan 5, 2017
Priority date	Apr 20, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes interlayer support patterns sequentially stacked on a substrate, horizontal conductive patterns sequentially stacked on the substrate, and an interlayer insulating layer disposed between the interlayer support patterns, extending between the horizontal conductive patterns, and disposed in parallel with a surface of the substrate. The interlayer insulating layer is in contact with the interlayer support patterns. A conductive structure extends in a direction perpendicular to the substrate. Vertical structures extending through the horizontal conductive patterns and the interlayer insulating layer are formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a stack of interlayer support patterns on a substrate;
a stack of horizontal conductive patterns on the substrate and disposed laterally of the stack of interlayer support patterns;
an interlayer insulating layer interposed between vertically adjacent ones of the interlayer support patterns in the stack of interlayer support patterns, extending between vertically adjacent ones of the horizontal conductive patterns in the stack of horizontal conductive patterns, and disposed parallel to a surface of the substrate, the interlayer insulating layer being in contact with the vertically adjacent ones of the interlayer support patterns;
a conductive structure extending in a direction perpendicular to said surface of the substrate;
first vertical structures each extending vertically through the vertically adjacent ones of the horizontal conductive patterns and the interlayer insulating layer extending between the vertically adjacent ones of the horizontal conductive patterns; and
second vertical structures each extending vertically through the vertically adjacent ones of the interlayer support patterns and the interlayer insulating layer extending between the vertically adjacent ones of the interlayer support patterns,
wherein each of the first vertical structures and each of the second vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

2. The semiconductor device of claim 1 , wherein the interlayer support patterns comprise insulating material of a composition different from that of the interlayer insulating layer.

3. The semiconductor device of claim 1 , wherein the first vertical structures comprise a first plurality of the first vertical structures and a second plurality of the first vertical structures spaced from the first plurality of the first vertical structures, and the conductive structure extends between the first plurality of the first vertical structures and the second plurality of the first vertical structures.

4. The semiconductor device of claim 3 , wherein the conductive structure includes a first portion and a second portion spaced from each other in a direction perpendicular to that in which the second plurality of the first vertical structures are spaced from the first plurality of the first vertical structures, and
the first portion and the second portion of the conductive structure each extend between the first plurality of the first vertical structures and the second plurality of the first vertical structures.

5. The semiconductor device of claim 4 , wherein at least one of the interlayer support patterns is interposed between the first portion and the second portion of the conductive structure.

6. The semiconductor device of claim 1 , further comprising a gate dielectric structure interposed between the first vertical structures and the vertically adjacent ones of the horizontal conductive patterns,
wherein the gate dielectric structure includes a data storage layer.

7. The semiconductor device of claim 1 , wherein the conductive structure extends vertically through the interlayer insulating layer and the horizontal conductive patterns, and further comprising an insulating spacer interposed between the conductive structure and the horizontal conductive patterns.

8. The semiconductor device of claim 1 , further comprising a source impurity region within the substrate at a bottom of the conductive structure.

9. A semiconductor device comprising:
first interlayer support patterns disposed on a substrate;
first horizontal conductive patterns disposed on the substrate;
a first interlayer insulating layer interposed between the first interlayer support patterns, in contact with the first interlayer support patterns, and extending between the first horizontal conductive patterns;
first vertical structures extending through the first interlayer insulating layer and the first horizontal conductive patterns;
a gate dielectric structure interposed between the first horizontal conductive patterns and the first vertical structures;
second interlayer support patterns interposed between the substrate and the first interlayer support patterns;
second horizontal conductive patterns interposed between the substrate and the first horizontal conductive patterns; and
a second interlayer insulating layer interposed between the second interlayer support patterns, in contact with the second interlayer support patterns, and extending between the second horizontal conductive patterns,
wherein the first vertical structures are vertically spaced apart from the second interlayer insulating layer, and
each of the first vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

10. The semiconductor device of claim 9 , wherein the first interlayer support patterns, the first horizontal conductive patterns, the first interlayer insulating layer, and the first vertical structures are disposed on an edge chip area of the substrate.

11. The semiconductor device of claim 10 , further comprising:
main interlayer insulating layers and main horizontal conductive patterns alternately stacked on a main chip area of the substrate; and
main vertical structures extending through the main interlayer insulating layers and the main horizontal conductive patterns,
wherein the edge chip area is closer to an edge of the substrate than the main chip area.

12. The semiconductor device of claim 11 , further comprising:
a main conductive structure disposed on the main chip area of the substrate; and
an edge conductive structure disposed on the edge chip area of the substrate,
wherein the main conductive structure is provided at an arrangement density higher than that of the edge conductive structure.

13. The semiconductor device of claim 9 , further comprising second vertical structures extending through the first interlayer insulating layer and the first interlayer support patterns,
wherein the second vertical structures are vertically spaced apart from the second interlayer insulating layer, and
each of the second vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

14. A semiconductor device comprising:
a substrate;
horizontal interlayer support patterns, of insulating material, disposed one above another on a first region of the substrate;
horizontal conductive patterns disposed one above another on a second region of the substrate,
wherein a respective one of the horizontal interlayer support patterns and a respective one of the horizontal conductive patterns are laterally juxtaposed at each of a plurality of levels above the substrate;
interlayer insulating layers disposed one above another on the substrate and each spanning the first and second regions of the substrate, each of the interlayer insulating layers being interposed between vertically adjacent ones of the horizontal interlayer support patterns above the first region of the substrate and between adjacent ones of the horizontal conductive patterns above the second region of the substrate;
first pillars each extending vertically through at least uppermost ones of the horizontal conductive patterns and the interlayer insulating layers on the second region of the substrate; and
second pillars each extending vertically through uppermost ones only of the interlayer support patterns and the interlayer insulating layers on the first region of the substrate such that each of the second pillars is vertically spaced apart from lowermost o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Jang Gn
• Kim Sun Young

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H10B43/23

  with source and drain on different levels, e.g. with sloping channels · CPC title

• H10B41/42

  Simultaneous manufacture of periphery and memory cells · CPC title