Semiconductor device

Patent metadata

Field	Value
Publication number	US-9978769-B2
Application number	US-201615066190-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Nov 20, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; a plate portion; and a sidewall insulating film. The thermal expansion coefficient of the substrate is α1. The stacked body includes a plurality of electrode layers and a memory cell array. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a first layer and a second layer. The thermal expansion coefficient of the first layer is the α 2 being different from the α 1 . The thermal expansion coefficient of the second layer is the α 3 being different from the α 2 . The value of the α 3 is in a direction from the value of the α 2 toward the value of the α 1 . The second layer faces the major surface of the substrate continuously in the memory cell array.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a major surface, a thermal expansion coefficient of the substrate being α 1 ;
a stacked body provided on the major surface of the substrate, the stacked body including a plurality of electrode layers and a memory cell array, the plurality of electrode layers stacked with an insulator interposed;
a columnar portion provided in the stacked body, the columnar portion extending along a stacking direction of the stacked body, the columnar portion including a semiconductor body and a charge storage film, the charge storage film provided between the semiconductor body and the electrode layer;
a plate portion provided in the stacked body, the plate portion extending along the stacking direction of the stacked body and a first direction crossing the stacking direction, the plate portion including a first layer and a second layer, a thermal expansion coefficient of the first layer being α 2 , a thermal expansion coefficient of the second layer being α 3 , the α 2 being different from the α 1 the α 3 being different from the α 2 , wherein
when a relationship between a value of the α 1 and a value of the α 2 is α 1 <α 2 , a value of the thermal expansion coefficient α 3 is α 3 <α 2 , otherwise
when a relationship between a value of the α 1 and a value of the α 2 is α 1 >α 2 , a value of the thermal expansion coefficient α 3 is α 3 >α 2 ,

the first layer and the second layer stacked along the stacking direction of the stacked body, the second layer provided between the first layer and the major surface of the substrate, the second layer facing the major surface of the substrate continuously in the memory cell array; and
a sidewall insulating film provided in the stacked body, the sidewall insulating film provided between the stacked body and the plate portion,
wherein the stacked body includes a first stairstep structure portion and a second stairstep structure portion,
wherein the first stairstep structure portion and the second stairstep structure portion are provided respectively along one set of opposite sides of the memory cell array, and
wherein the plate portion is provided to cross through the memory cell array from the first stairstep structure portion to the second stairstep structure portion.

2. The semiconductor device according to claim 1 , wherein
the first layer includes a first conductor, and
the second layer includes an insulator.

3. The semiconductor device according to claim 1 , wherein
the first layer includes a first conductor, and
the second layer includes a second conductor different from the first conductor.

4. The semiconductor device according to claim 3 , wherein a major component included in the substrate is the same as a major component included in the second layer.

5. The semiconductor device according to claim 4 , wherein
the substrate includes silicon as the major component, and
the second layer includes silicon as the major component.

6. The semiconductor device according to claim 5 , wherein a conductivity type of the second layer is the same as a conductivity type of the substrate.

7. The semiconductor device according to claim 1 , wherein the plate portion includes a first barrier film between the sidewall insulating film and a side surface of the plate portion and between a bottom surface of the plate portion and the major surface of the substrate.

8. The semiconductor device according to claim 7 , wherein the plate portion includes a second barrier film between the first layer and the first barrier film and between the first layer and the second layer.

9. The semiconductor device according to claim 1 , wherein the plate portion includes a barrier film between the first layer and the sidewall insulating film and between the first layer and the second layer.

Assignees

• Toshiba Memory Corp

Inventors

• Shimura Yasuhiro

Classifications

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H01L27/11558

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11529

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic