Broadcast channel architectures for block-based processors
US-10452399-B2 · Oct 22, 2019 · US
Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F9/268 |
| Official title | {Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs} |
| Display label | Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs |
| Total patents | 116 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 5 |
| 2016 | 7 |
| 2017 | 30 |
| 2018 | 13 |
| 2019 | 11 |
| 2020 | 14 |
| 2021 | 9 |
| 2022 | 12 |
| 2023 | 10 |
| 2024 | 2 |
| 2025 | 1 |
| 2026 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Multimodal targets in a block-based processor
US-10445097-B2 · Oct 15, 2019 · US
Hint instruction for managing transactional aborts in transactional memory computing environments
US-2019138346-A1 · May 9, 2019 · US
Hint instruction for managing transactional aborts in transactional memory computing environments
US-10210019-B2 · Feb 19, 2019 · US
Write nullification
US-10198263-B2 · Feb 5, 2019 · US
Apparatus and method for system physical address to memory module address translation
US-10162761-B2 · Dec 25, 2018 · US
Scheduler for amp architecture using a closed loop performance and thermal controller
US-2018349175-A1 · Dec 6, 2018 · US
Scheduler for amp architecture using a closed loop performance controller and deferred inter-processor interrupts
US-2018349177-A1 · Dec 6, 2018 · US
Scheduler for AMP Architecture with Closed Loop Performance Controller Using Static and Dynamic Thread Grouping
US-2018349186-A1 · Dec 6, 2018 · US
Scheduler for amp architecture using a closed loop performance and thermal controller
US-2018349191-A1 · Dec 6, 2018 · US
Scheduling of work interval objects in an amp architecture using a closed loop performance controller
US-2018349182-A1 · Dec 6, 2018 · US
Scheduler for amp architecture with closed loop performance controller
US-2018349176-A1 · Dec 6, 2018 · US
Multi-nullification
US-2018329708-A1 · Nov 15, 2018 · US
Instruction block address register
US-10095519-B2 · Oct 9, 2018 · US
Data processor device supporting selectable exceptions and method thereof
US-10073797-B2 · Sep 11, 2018 · US
Power-down interrupt of nonvolatile dual in-line memory system
US-10073744-B2 · Sep 11, 2018 · US
Store nullification in the target field
US-10061584-B2 · Aug 28, 2018 · US
Multi-nullification
US-10031756-B2 · Jul 24, 2018 · US
Microprocessor using compressed and uncompressed microcode storage
US-9830155-B2 · Nov 28, 2017 · US
Propagation of microcode patches to multiple cores in multicore microprocessor
US-9792112-B2 · Oct 17, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F9/268?
- CPC G06F9/268 is the Cooperative Patent Classification code for “Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs.”
- How many patents are filed under CPC G06F9/268 (Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs)?
- Our database includes 116 publications tagged with this CPC code.
- Is patent activity under CPC G06F9/268 growing?
- Publication counts under this code: 2 in 2024 vs 1 in 2025 (latest complete years).