Microprocessor using compressed and uncompressed microcode storage

Patent metadata

Field	Value
Publication number	US-9830155-B2
Application number	US-201615140010-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Oct 18, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A microprocessor includes compressed and uncompressed microcode memory storages, having N-bit wide and M-bit wide addressable words, respectively, where N<M. The microprocessor also includes a fetch unit, an instruction translator, and an execution stage. When the instruction translator receives an architectural instruction, it writes information identifying source and destination registers specified by the architectural instruction to an indirection register. It also issues one or more fetch addresses to retrieve a sequence of one or more microcode instructions from one of the uncompressed microcode memory storage and the compressed microcode memory storage to implement the architectural instruction. It merges information in the indirection register with the sequence of one or more microcode instructions to generate a sequence of one or more implementing microinstructions.

First claim

The invention claimed is:

1. A microprocessor comprising:
a fetch unit operative to fetch architectural instructions from memory;
an uncompressed microcode memory storage having M-bit wide addressable words;
a compressed microcode memory storage having N-bit wide addressable words, where N<M;
an instruction translator operative to receive the architectural instructions supplied by the fetch unit and translate them into microinstructions executable according to a microinstruction set architecture of the microprocessor; and
an execution stage operative to receive microinstructions from the instruction translator and execute them;
wherein when the instruction translator receives an architectural instruction, it:
writes information identifying source and destination registers specified by the architectural instruction to an indirection register;
issues one or more fetch addresses to retrieve a sequence of one or more microcode instructions from one of the uncompressed microcode memory storage and the compressed microcode memory storage to implement the architectural instruction;
merges information in the indirection register with the sequence of one or more microcode instructions to generate a sequence of one or more implementing microinstructions;

a plurality of cores, each core having a corresponding core ROM that is private to the core;
an uncore ROM shared by the plurality of cores;
arbitration logic configured to arbitrate among the cores when they request access to the uncore ROM; and
wherein each core is configured to fetch microcode instructions from its own core ROM and the uncore ROM.

2. The microprocessor of claim 1 , wherein when the instruction translator receives an architectural instruction, it also decompresses the microcode instructions, if compressed, before merging them with information stored in the indirection register.

3. The microprocessor of claim 1 , further comprising a single read port for the uncore ROM, which is shared by all the cores, and arbitration logic that grants use of the read port by the cores according to an arbitration algorithm.

4. The microprocessor of claim 1 , wherein:
the uncore ROM provides a maximum storage capacity of J words, each word having a width of an uncompressed microcode instruction, which is M bits;
each of the core ROMs provides a maximum storage capacity of K words, each word having a width of a compressed microcode instruction, which is N bits;
wherein the J words of the uncore ROM reside at different address locations of a microcode memory address space than the K words of any other core ROM.

5. The microprocessor of claim 1 , wherein the instruction translator further comprises a decompression unit configured to decompress compressed microcode instructions stored in the compressed microcode memory storage before they are merged with information stored in the indirection register.

6. The microprocessor of claim 5 , wherein:
the decompression unit comprises a decompressor, a buffer, and control logic;
wherein the buffer receives subsets of bits of microcode instruction words;
wherein the control logic, if it detects that a multi-word uncompressed binary microcode instruction is split between at least first and second words of the compressed microcode storage, causes the buffer to join at least a first subset of bits of the first word to a second subset of bits of the second word to regenerate the uncompressed microcode instruction.

7. The microprocessor of claim 1 , wherein when the instruction translator receives an architectural instruction, it also writes displacement, immediate, and constant fields, if any, for each source operand to the indirection register.

8. The microprocessor of claim 1 , wherein when the instruction translator receives an architectural instruction, it also writes information to indicate the first and last microinstruction in the sequence of microinstructions that implement the architectural instruction to the indirection register.

9. A method of translating instructions comprising:
receiving architectural instructions fetched from memory;
writing information identifying source and destination registers specified by the architectural instructions to an indirection register;
issuing fetch addresses to retrieve sequences of microcode instructions from an uncompressed microcode memory storage and a compressed microcode memory storage to implement the architectural instructions, wherein the uncompressed and compressed microcode memory storages have M-bit wide and N-bit wide addressable words, respectively, where N<M;
merging information in the indirection register with the sequences of microcode instructions to generate sequences of implementing microinstructions;
wherein the act of translating instructions is performed in a microprocessor comprising a plurality of cores, each core having a corresponding core ROM that is private to the core, the microprocessor further comprising an uncore ROM shared by the plurality of cores and arbitration logic configured to arbitrate among the cores when they request access to the uncore ROM, the method further comprising:
each core fetching microcode instructions from its own core ROM and the uncore ROM.

10. The method of claim 9 , further comprising decompressing compressed microcode instructions stored in the compressed microcode memory storage before they are merged with information stored in the indirection register.

11. The method of claim 10 , wherein the act of decompressing comprises:
receiving subsets of bits of microcode instruction words; and
detecting whether a multi-word uncompressed binary microcode instruction is split between at least first and second words of the compressed microcode storage, and if so joining at least a first subset of bits of the first word to a second subset of bits of the second word to regenerate the uncompressed microcode instruction.

12. The method of claim 9 , wherein the microprocessor further comprises a single read port for the uncore ROM, which is shared by all the cores, the method further comprising arbitration logic granting use of the read port by the cores according to an arbitration algorithm.

13. The method of claim 9 , wherein the uncore ROM provides a maximum storage capacity of J words, each word having a width of an uncompressed microcode instruction, which is M bits, and each of the core ROMs provides a maximum storage capacity of K words, each word having a width of a compressed microcode instruction, which is N bits, the method further comprising:
storing the J words of the uncore ROM reside at different address locations of a microcode memory address space than the K words of any other core ROM.

14. The method of claim 9 , further comprising writing displacement, immediate, and constant fields, if any, for each source operand of received architectural instructions to the indirection register.

15. The method of claim 9 , further comprising writing information to indicate the first and last microinstruction in the sequence of microinstructions that implement the architectural instruction to the indirection register.

Assignees

• Via Tech Inc

Inventors

• Henry G Glenn
• Parks Terry
• Bean Brent

Classifications

• G06F9/30178 Primary

  of compressed or encrypted instructions · CPC title

• G06F9/28

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/268

  Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs · CPC title

• G06F9/26

  Address formation of the next micro-instruction (G06F9/28 takes precedence){; Microprogram storage or retrieval arrangements} · CPC title