Power-down interrupt of nonvolatile dual in-line memory system

Patent metadata

Field	Value
Publication number	US-10073744-B2
Application number	US-201615244745-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Mar 28, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A nonvolatile memory module includes volatile memory devices; a nonvolatile memory device; and a controller suitable for backing up data stored in the volatile memory devices or restoring data backed up in the nonvolatile memory device, according to a fail/recovery of power of the host, the controller including a power-down interrupt logic which interrupts a backup operation when the power of the host is recovered while performing the backup operation, the power-down interrupt logic including: a logic which determines whether sufficient erased blocks exist in the nonvolatile memory device; a logic which erases a new block when the sufficient erased bocks do not exist; and an interrupt backup logic which backs up a volatile memory device having data corresponding to the erased block, when a fail in the power of the host is detected or a backup operation is instructed from the host.

First claim

What is claimed is:

1. A nonvolatile memory module comprising:
a plurality of volatile memory devices sharing a data bus through which data is transmitted and a control bus through which a command and an address are transmitted;
at least one nonvolatile memory device; and
a controller configured to back up data stored in the plurality of volatile memory devices in the nonvolatile memory device or restore data backed up in the nonvolatile memory device to the plurality of volatile memory devices, according to a fail/recovery of power of a host, the controller including a power-down interrupt logic configured to interrupt a backup operation when the power of the host is recovered while performing the backup operation,
the power-down interrupt logic comprising:
a logic configured to determine whether a sufficient amount of erased blocks for data backup exist in the nonvolatile memory device, to prepare for a fail in the power of the host;
a logic configured to erase a new block when the sufficient amount of erased blocks do not exist in the nonvolatile memory device; and
an interrupt backup logic configured to
set a command address latency (CAL) for identifying the volatile memory device having the data corresponding to the erased block among the plurality of volatile memory devices which share the data bus and the control bus, to a first value;
set a command address latency of remaining volatile memory devices among the plurality of volatile memory devices, to a second value different from the first value;
read the volatile memory by using the setting value of the command address latency (CAL); and
back up a volatile memory device having data corresponding to an erased block of the nonvolatile memory device, in the nonvolatile memory device, when a fail in the power of the host is detected or a backup operation is instructed from the host.

2. The nonvolatile memory module according to claim 1 , wherein the second value is greater than the first value, and a difference between the second value and the first value is equal to or greater than a row address to column address delay time (tRCD: RAS to CAS delay).

3. The nonvolatile memory module according to claim 2 , wherein the difference between the second value and the first value is less than a row precharge time (tRP).

4. The nonvolatile memory module according to claim 1 , wherein the controller resumes the backup operation interrupted by the power-down interrupt logic, after performing the backing up by the interrupt backup logic.

5. The nonvolatile memory module according to claim 1 , wherein the controller resumes the backup operation interrupted by the power-down interrupt logic, after performing the backing up by the interrupt backup logic.

6. The nonvolatile memory module according to claim 2 , wherein the controller resumes the backup operation interrupted by the power-down interrupt logic, after performing the backing up by the interrupt backup logic.

7. The nonvolatile memory module according to claim 3 , wherein the controller resumes the backup operation interrupted by the power-down interrupt logic, after performing the backing up by the interrupt backup logic.

8. The nonvolatile memory module according to claim 1 , wherein the interrupt backup logic comprises:
a logic configured to perform a distributed refresh operation for uniformly distributing a refresh cycle over the plurality of volatile memory devices while programming a memory page of the nonvolatile memory device;
a logic configured to operate the plurality of volatile memory devices under a low power mode having a power lower than a power of a complete operation state, while a new memory page of the nonvolatile memory device is prepared and written; and
a logic configured to recover the plurality of volatile memory devices to a power mode of the complete operation state after the new memory page of the nonvolatile memory device is written.

9. The nonvolatile memory module according to claim 1 , wherein the interrupt backup logic comprises:
a logic configured to perform a distributed refresh operation for uniformly distributing a refresh cycle over the plurality of volatile memory devices while programming a memory page of the nonvolatile memory device;
a logic configured to operate the plurality of volatile memory devices under a low power mode having a power lower than a power of a complete operation state, while a new memory page of the nonvolatile memory device is prepared and written; and
a logic configured to recover the plurality of volatile memory devices to a power mode of the complete operation state after the new memory page of the nonvolatile memory device is written.

10. The nonvolatile memory module according to claim 2 , wherein the interrupt backup logic comprises:
a logic configured to perform a distributed refresh operation for uniformly distributing a refresh cycle over the plurality of volatile memory devices while programming a memory page of the nonvolatile memory device;
a logic configured to operate the plurality of volatile memory devices under a low power mode having a power lower than a power of a complete operation state, while a new memory page of the nonvolatile memory device is prepared and written; and
a logic configured to recover the plurality of volatile memory devices to a power mode of the complete operation state after the new memory page of the nonvolatile memory device is written.

11. The nonvolatile memory module according to claim 3 , wherein the interrupt backup logic comprises:
a logic configured to perform a distributed refresh operation for uniformly distributing a refresh cycle over the plurality of volatile memory devices while programming a memory page of the nonvolatile memory device;
a logic configured to operate the plurality of volatile memory devices under a low power mode having a power lower than a power of a complete operation state, while a new memory page of the nonvolatile memory device is prepared and written; and
a logic configured to recover the plurality of volatile memory devices to a power mode of the complete operation state after the new memory page of the nonvolatile memory device is written.

12. A method for operating a nonvolatile memory module including a plurality of volatile memory devices which share a data bus through which data is transmitted and a control bus through which a command and an address are transmitted, a nonvolatile memory device, and a controller which backs up data stored in the plurality of volatile memory devices in the nonvolatile memory device or restores data backed up in the nonvolatile memory device to the plurality of volatile memory devices, according to a fail/recovery of power of a host, the method comprising:
interrupting, by the controller, a backup operation when the power of the host is recovered while performing the backup operation;
determining, by the controller, whether a sufficient amount of erased blocks for data backup exist in the nonvolatile memory device, to prepare for a fail in the power of the host which may occur;
erasing, by the controller, a new block when the sufficient amount of erased bocks do not exist in the nonvolatile memory device; and
backing up, by the controller, a volatile memory device having data corresponding to an erased block of the nonvolatile memory device, in the nonvolatile memory device, when a fail in the power of the host is detected or a backup operation is instructed from the host,
wherein the backing up of the volatile memory device comprises:
setting a command address latency (CAL) for identifying the volatile memory device having the data corresponding to the erased block among

Assignees

• Sk Hynix Inc

Inventors

• Yoon Hyunju

Classifications

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F11/1451 Primary

  by selection of backup contents · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G06F11/1456 Primary

  Hardware arrangements for backup · CPC title

• G11C14/0009

  in which the volatile element is a DRAM cell · CPC title