In-memory full adder

Patent metadata

Field	Value
Publication number	US-11604850-B2
Application number	US-202016740584-A
Country	US
Kind code	B2
Filing date	Jan 13, 2020
Priority date	Dec 6, 2016
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.

First claim

What is claimed is:

1. An in-memory full adder comprising:
a memory array having a plurality of rows and columns, at least one said column being connected by a bit line, said at least one column storing a first bit in a first row of said bit line, a second bit in a second row of said bit line, and an inverse of a carry-in bit in a third row of said bit line;
a full adder unit to store, in said second and third rows of said bit line, a sum bit and a carry out bit output, respectively, of adding said first bit, said second bit and said carry-in bit, said full adder unit not to overwrite any of said bits when a full adder table indicates that said sum bit and said carry out bit are equivalent to said second bit and said carry-in bit.

2. The adder of claim 1 and wherein said full adder unit comprises:
a computation table to store a set of change trigger sequences, and an associated value for said sum and carry-out bits per sequence;
a row decoder to activate said first, said second and said third rows according to said set of change trigger sequences, one current sequence at a time; and
a column decoder to receive a compare result from said bit line indicating a match of data stored in said column to said current change trigger sequence,
said row decoder to activate a sum row and a carry-out row of said memory array and said column decoder to write a sum bit and a carry-out bit associated with said current change trigger sequence in said sum row and said carry-out row through said bit line if said compare result indicates a match.

3. The adder of claim 2 wherein said set of change trigger sequences are 000, 010, 111 and 101 and their associated values for the sum and carry-out bits are 1, 0, 0 and 1 respectively.

4. The adder of claim 1 and wherein said full adder unit operates on said plurality of columns in parallel.

Assignees

• Gsi Technology Inc

Inventors

• Shu Leelean
• Akerib Avidan

Classifications

• G06F7/506

  with simultaneous carry generation for, or propagation over, two or more stages · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/4824

  using signed-digit representation · CPC title

• G06F17/11 Primary

  for solving equations {, e.g. nonlinear equations, general mathematical optimization problems (optimization specially adapted for a specific administrative, business or logistic context G06Q10/04)} · CPC title