Computing array based on 1T1R device, operation circuits and operating methods thereof

Patent metadata

Field	Value
Publication number	US-11475949-B2
Application number	US-201816336900-A
Country	US
Kind code	B2
Filing date	Jun 7, 2018
Priority date	Dec 17, 2017
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

First claim

What is claimed is:

1. A computing array based on 1T1R device, comprising: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays,
wherein 16 basic Boolean logic operations are implemented by controlling initial resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals;
a logic signal stored in the 1T1R device is read by inputting a logic signal V WL =1 via a word line, a logic signal V BL =V read via a bit line and a logic signal V SL =0 via a source line; V read is a voltage pulse signal applied when a resistance state of the 1T1R device is read.

2. The computing array based on 1T1R device according to claim 1 , wherein the 1T1R array includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; resistance states of the 1T1R devices include: High Resistance H and Low Resistance L; the 1T1R devices realize storage and processing of information through different resistance states; and the 1T1R devices in the same row are connected to the same word line, the 1T1R devices in the same column are connected to the same bit line and source line, and through applying different signals to the word lines WL, the bit lines BL and the source lines SL, different operations are achieved and operation results are stored.

3. The computing array based on 1T1R device according to claim 2 , wherein the 1T1R device includes a transistor and a resistive element; the transistor includes a substrate, a source, a drain, an insulating layer and a gate, in which the source is connected to the source line SL, and the gate is connected to the word line WL; the resistive element includes two end electrodes, one of which is connected to the bit line BL and the other of which is connected to the drain of the transistor; and the resistive element has a stacked structure with a nonvolatile resistance transition characteristic.

4. The computing array based on 1T1R device according to claim 2 , wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit;
the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result;
an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array;
an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array;
an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array;
the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array;
an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modern;
a first input terminal of the control signal modern is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array;
an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.

5. The computing array based on 1T1R device according to claim 3 , wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit;
the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result;
an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the

Assignees

• Univ Huazhong Science Tech

Inventors

• Li Yi
• Wang Zhuorui
• Miao Xiangshui
• Zhou Yaxiong
• Cheng Long

Classifications

• G11C2213/82

  Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title