Adder circuitry for very large integers

Patent metadata

Field	Value
Publication number	US-11662979-B2
Application number	US-202016953135-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Jul 12, 2018
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first adder circuit configured to generate a first sum and first carry bits;
a second adder circuit configured to generate a second sum and second carry bits;
a third adder circuit configured to receive the first and second sums; and
counter circuitry configured to receive the first carry bits and the second carry bits.

2. The integrated circuit of claim 1 , wherein the third adder circuit does not include any inputs for receiving the first and second carry bits.

3. The integrated circuit of claim 1 , further comprising:
a fourth adder circuit configured to generate a third sum and third carry bits;
a fifth adder circuit configured to generate a fourth sum and fourth carry bits; and
a sixth adder circuit configured to receive the third and fourth sums, wherein the counter circuitry is further configured to receive the third carry bits and the fourth carry bits.

4. The integrated circuit of claim 3 , wherein:
the third adder circuit is devoid of inputs for receiving the first and second carry bits; and
the sixth adder circuit is devoid of inputs for receiving the third and fourth carry bits.

5. The integrated circuit of claim 3 , wherein the counter circuitry is configured to count a total number of high bits in the first, second, third, and fourth carry bits.

6. The integrated circuit of claim 3 , further comprising:
means for combining carry bits output from the third adder circuit and the sixth adder circuit.

7. The integrated circuit of claim 3 , further comprising:
means for combining carry bits output from the third adder circuit and the sixth adder circuit and count values output from the counter circuitry.

8. The integrated circuit of claim 3 , further comprising:
a seventh adder circuit configured to receive sums output from the third adder circuit and the sixth adder circuit.

9. The integrated circuit of claim 1 , wherein the first adder circuit comprises:
a first sub-adder circuit configured to generate a first portion of the first sum;
a second sub-adder circuit configured to generate a second portion of the first sum;
a third sub-adder circuit configured to generate a third portion of the first sum; and
a fourth sub-adder circuit configured to generate a fourth portion of the first sum.

10. The integrated circuit of claim 9 , wherein the first adder circuit further comprises:
a prefix network configured to receive propagate and generate bits from the first, second, and third sub-adder circuits and to output the first carry bits.

11. An integrated circuit, comprising:
a first adder circuit having a first sum output and first carry outputs;
a second adder circuit having a second sum output and second carry outputs; and
a third adder circuit having a first input coupled to the first sum output and a second input coupled to the second sum output, the third adder circuit being configured to compute a sum without using signals from the first and second carry outputs.

12. The integrated circuit of claim 11 , further comprising:
a first counter circuit having a first input coupled to a first portion of the first carry outputs and having a second input coupled to a first portion of the second carry outputs.

13. The integrated circuit of claim 12 , further comprising:
a second counter circuit having a first input coupled to a second portion, different than the first portion, of the first carry outputs and having a second input coupled to a second portion, different than the first portion, of the second carry outputs.

14. The integrated circuit of claim 13 , further comprising:
a third counter circuit having a first input coupled to a third portion, different than the first and second portions, of the first carry outputs and having a second input coupled to a third portion, different than the first and second portions, of the second carry outputs.

15. The integrated circuit of claim 14 , wherein the first, second, and third counters are configured to count a total number of high bits generated on the first and second carry outputs.

16. An apparatus, comprising:
a sum pipeline having a sum output; and
a carry pipeline configured to receive carry bits from the sum pipeline, wherein the sum pipeline is configured to compute the sum output without using the carry bits.

17. The apparatus of claim 16 , further comprising:
an additional sum pipeline having an additional sum output; and
an adder circuit having a first input coupled to the additional sum output, a second input coupled to the carry pipeline, and an adder output.

18. The apparatus of claim 17 , further comprising:
a summing block having a first input coupled to the sum output and a second input coupled to the adder output.

19. The apparatus of claim 17 , further comprising:
an additional carry pipeline configured to receive additional carry bits from the additional sum pipeline, wherein the additional sum pipeline is configured to compute the additional sum output without using the additional carry bits.

20. The apparatus of claim 16 , wherein:
the sum pipeline comprises at least a first sub-adder circuit configured to combine bits from first and second input operands and a second sub-adder circuit configured to combine bits from third and fourth input operands different than the first and second input operands; and
the carry pipeline comprises at least one counter.

Assignees

• Intel Corp

Inventors

• Langhammer Martin

Classifications

• G06F7/503 Primary

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title

• H03K19/17744 Primary

  for input/output signals · CPC title

• H03K19/17724

  Structural details of logic blocks · CPC title

• G06F2207/4812

  Multiplexers · CPC title

• G06F2207/5063

  2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder · CPC title