FPGA logic cell with improved support for counters

Patent metadata

Field	Value
Publication number	US-10936286-B2
Application number	US-201916242998-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Nov 13, 2018
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

First claim

What is claimed is:

1. A logic cell for a programmable logic integrated circuit comprising:
K data inputs;
a primary output;
a carry-in input;
a carry-out output;
a counter input;
a sum output;
a K-input lookup table (LUT) having K LUT inputs each connected to a different one of the K data inputs, and a LUT output directly connected to the primary output, the K-input LUT including:
a first (K- 1 )-input lookup table LUT and a second (K- 1 )-input LUT both sharing in common second through Kth inputs to the K-input LUT, each of the first and second (K- 1 )-input LUTs having an output;
a first multiplexer having a first input coupled to the output of the first (K- 1 )-input LUT, a second data input coupled to the output of the second (K- 1 )-input LUT, and a select input coupled to a first input of the K-input LUT, the first multiplexer having an output forming the LUT output that is directly connected to the primary output; and

a carry circuit comprising:
a second multiplexer having a first data input coupled to the output of one of the first and second (K- 1 )-input LUTs, a second data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell, and a data output;
a third multiplexer having a first data input coupled to the counter input of the logic cell, a second data input coupled to the LUT output, a third data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell, and a data output;
a carry-out multiplexer having a first data input coupled to the data output of the second multiplexer, a second data input coupled to the carry-in input of the logic cell, a select input coupled to the data output of the third multiplexer, and a data output coupled to the carry-out output of the logic cell; and
an exclusive-OR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the data output of the third multiplexer, and an output coupled to the sum output of the logic cell.

2. The logic cell of claim 1 wherein the carry circuit further comprises:
a fourth multiplexer coupled between the counter input of the logic cell and the first data input of the third multiplexer, the fourth multiplexer having a first data input and a second data input, the second data input being an inverting data input, the first and second data inputs coupled together to the counter-input of the logic cell, a select input coupled to configuration circuitry for the logic cell, and an output coupled to the first data input of the third multiplexer.

3. The logic cell of claim 1 wherein at least one of the second and third multiplexers has a data input coupled to a logic-high constant voltage.

4. The logic cell of claim 1 wherein the second multiplexer has a data input coupled to the output of the first (K- 1 )-input LUT and a data input coupled to the output of the second (K- 1 )-input LUT.

5. A logic cell for a programmable logic integrated circuit comprising:
a first data input and a plurality of additional data inputs;
a first lookup table (LUT) having an output and a plurality of inputs, each of the plurality of inputs of the first LUT connected to a respective one of the plurality of additional data inputs;
a second LUT having an output and a plurality of inputs, each of the plurality of inputs of the second LUT connected to a respective one of the plurality of additional data inputs;
a first multiplexer having a first input coupled to the output of the first LUT, a second input coupled to the output of the second LUT, and a select input coupled to the first data input, the first multiplexer having an output that is directly connected to a primary output of the logic cell;
a second multiplexer having a first data input coupled to the output of the second LUT, a second data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell and a data output;
a third multiplexer having a first data input coupled to a counter input of the logic cell, a second data input coupled to the primary output of the logic cell, a third data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell and a data output;
a carry-out multiplexer having a first data input coupled to the data output of the second multiplexer, a second data input coupled to a carry-in input of the logic cell, a select input coupled to the data output of the third multiplexer and a data output coupled to a carry-out output of the logic cell; and
an exclusive-OR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the data output of the third multiplexer, and an output coupled to a sum output of the logic cell.

Assignees

• Microsemi Soc Corp

Inventors

• Greene Jonathan W
• Landry Joel

Classifications

• H03K19/215

  using field-effect transistors · CPC title

• H03K21/10

  comprising logic circuits · CPC title

• G06F7/506 Primary

  with simultaneous carry generation for, or propagation over, two or more stages · CPC title

• H03K19/17744

  for input/output signals · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title