Writing method and erasing method of fusion memory
US-12002500-B2 · Jun 4, 2024 · US
US9997227B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9997227-B2 |
| Application number | US-201514975439-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 18, 2015 |
| Priority date | Dec 18, 2015 |
| Publication date | Jun 12, 2018 |
| Grant date | Jun 12, 2018 |
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Described is an apparatus which comprises: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type FE-FETs, the second inverter having an input coupled to an output of the first inverter.
Opening claim text (preview).
We claim: 1. An apparatus comprising: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type ferroelectric field effect transistors (FE-FETs), the second inverter having an input coupled to an output of the first inverter, wherein the first power domain is separate from the second power domain. 2. The apparatus of claim 1 , wherein the second inverter is to hold a logic state at gate terminals of the p-type and n-type FE-FETs when the first power domain is powered down by switching off the first switchable positive and negative supplies. 3. The apparatus of claim 1 , wherein the second inverter is to hold a logic state at gate terminals of the p-type and n-type FE-FETs when the first switchable positive and switchable supplies are to be set to zero supplies, respectively. 4. The apparatus of claim 1 , wherein the first inverter includes p-type and n-type MOSFETs coupled to the p-type and n-type FE-FETs, respectively. 5. The apparatus of claim 1 , wherein the first switchable positive power supply is to switch between a positive supply and zero supply. 6. The apparatus of claim 1 , wherein the first switchable negative power supply is to switch between a negative supply and zero supply. 7. The apparatus of claim 1 , wherein the second inverter is to be powered by a second switchable positive supply and a second switchable negative supply such that second switchable positive supply is to be provided to a p-type FE-FET of the second inverter, and wherein the second switchable negative supply is to be provided to an n-type FE-FET of the second inverter. 8. The apparatus of claim 1 , wherein the first power domain is separate from the second power domain.
by using a control or a clock signal, e.g. in order to apply power supply · CPC title
using ferroelectric capacitors · CPC title
using MOS with ferroelectric gate insulating film · CPC title
using galvano-magnetic devices, e.g. Hall-effect devices · CPC title
Power supply circuits · CPC title
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