Apparatuses having a ferroelectric field-effect transistor memory array and related method

Patent metadata

Field	Value
Publication number	US-9786684-B2
Application number	US-201615379933-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	May 17, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a three-dimensional memory array including:
a first source region, a first body region, and a first drain region arranged vertically in a first vertical stack, and extending in a first direction;
a first dielectric material disposed on the first vertical stack and extending in the first direction;
a second source region, a second body region, and a second drain region arranged vertically in a second vertical stack disposed on the first dielectric material, and extending in the first direction;
a first ferroelectric material disposed adjacent to both the first vertical stack and the second vertical stack;
a first gate disposed adjacent to the first ferroelectric material, and extending in a second direction forming a first ferroelectric FET (FeFET) with the first vertical stack and a second FeFET with the second vertical stack; and
a second gate, offset from the first gate in the first direction, and disposed adjacent to the first ferroelectric material and extending in the second direction forming a third FeFET with the first vertical stack and a fourth FeFET with the second vertical stack.

2. The semiconductor memory device of claim 1 , wherein the three-dimensional memory array further includes:
a third source region, a third body region, and a third drain region arranged vertically in a third vertical stack, and extending in the first direction;
a second dielectric material disposed on the third vertical stack and extending in the first direction;
a fourth source region, a fourth body region, and a fourth drain region arranged vertically in a fourth vertical stack disposed on the second dielectric material, and extending in the first direction;
a second ferroelectric material disposed adjacent to both the third vertical stack and the fourth vertical stack;
a third gate disposed adjacent to the second ferroelectric material, and extending in a second direction forming a fifth FeFET with the third vertical stack and a sixth FeFET with the third vertical stack; and
a fourth gate, offset from the third gate in the first direction, and disposed adjacent to the second ferroelectric material and extending in the second direction forming a seventh FeFET with the fourth vertical stack and an eighth FeFET with the fourth vertical stack.

3. The semiconductor memory device of claim 2 , wherein the three-dimensional memory array further includes a third ferroelectric material extending along the third vertical stack and the fourth vertical stack, and adjacent to each of the first gate and the second gate forming:
a ninth FeFET with the third vertical stack and the first gate;
a tenth FeFET with the fourth vertical stack and the first gate;
an eleventh FeFET with the third vertical stack and the second gate; and
a twelfth FeFET with the fourth vertical stack and the second gate.

4. The semiconductor memory device of claim 2 , wherein the three-dimensional memory array further includes another material extending along the third vertical stack and the fourth vertical stack, and adjacent to each of the first gate and the second gate.

5. The semiconductor memory device of claim 2 , wherein the three-dimensional memory array further includes individual contacts coupled to each of the first gate, the second gate, the third gate, and the fourth gate such that each gate is part of a different word line.

6. The semiconductor memory device of claim 2 , wherein the three-dimensional memory array further includes:
a first contact coupled to both the first gate and the third gate such that each gate is part of a common word line; and
a second contact coupled to both the second gate and the fourth gate such that each gate is part of a different common word line.

7. A semiconductor memory device comprising:
a three-dimensional memory array, comprising:
a first gate, a second gate, and a third gate extending in a vertical direction in a first common plane;
a first source region, a first body region, and a first drain region arranged vertically in a first vertical stack;
a second source region, a second body region, and a second drain region arranged vertically in a second vertical stack;
a third source region, a third body region, and a third drain region arranged vertically in a third vertical stack;
a fourth source region, a fourth body region, and a fourth drain region arranged vertically in a fourth vertical stack;
a fifth source region, a fifth body region, and a fifth drain region arranged vertically in a fifth vertical stack; and
a sixth source region, a sixth body region, and a sixth drain region arranged vertically in a sixth vertical stack, wherein:
the first vertical stack and the second vertical stack are disposed adjacent to a first ferroelectric material disposed on a first side of the first gate;
the third vertical stack and the fourth vertical stack are adjacent to a second ferroelectric material disposed on a first side of the second gate; and
the fifth vertical stack and the sixth vertical stack are disposed adjacent to a third ferroelectric material disposed on a first side of the third gate.

8. The semiconductor memory device of claim 7 , wherein:
the third vertical stack and the fourth vertical stack are adjacent to a fourth ferroelectric material disposed on a second side of the first gate; and
the fifth vertical stack and the sixth vertical stack are disposed adjacent to a fifth ferroelectric material disposed on a second side of the second gate.

9. The semiconductor memory device of claim 8 , further comprising:
a seventh source region, a seventh body region, and a seventh drain region arranged vertically in a seventh vertical stack; and
an eighth source region, an eighth body region, and an eighth drain region arranged vertically in an eighth vertical stack, wherein the seventh vertical stack and the eighth vertical stack are disposed adjacent to a sixth ferroelectric material disposed on a second side of the third gate.

10. The semiconductor memory device of claim 7 , further comprising a fourth gate, a fifth gate, and a sixth gate extending in a vertical direction in a second common plane that is substantially parallel to the first common plane.

11. The semiconductor memory device of claim 10 , wherein the source regions, the body regions, and the drain regions for each of the vertical stacks and each of the ferroelectric materials extend in a direction transverse to the first common plane and the second common plane such that an FeFET is formed at each intersection of each of the vertical stacks and each of the ferroelectric materials with a respective gate.

12. The semiconductor memory device of claim 11 , further comprising:
a first dielectric material disposed between, and coextensive with, the first vertical stack and the second vertical stack;
a second dielectric material disposed between, and coextensive with, the third vertical stack and the fourth vertical stack; and
a third dielectric material disposed between, and coextensive with, the fifth vertical stack and the sixth vertical stack.

13. The semiconductor memory device of claim 7 , further comprising:
a first contact disposed on the three-dimensional memory array coupled with the first gate and the third gate and not the second gate; and
a second contact disposed on the three-dimensional memory array coupled with the second gate and not the first gate or the third gate.

14. The semiconductor memory device of claim 13 , wherein the first contact is disposed on a top portion of the three-dimensional memory array, and the second contact is disposed on a bott

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy D V Nirmal
• Johnson Adam D

Classifications

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/22

  using ferroelectric elements · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title