Three-dimensional ferroelectric FET-based structures

Patent metadata

Field	Value
Publication number	US-9818848-B2
Application number	US-201615140194-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Apr 29, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.

First claim

What is claimed is:

1. A three-dimensional Ferroelectric Field Effect Transistor (FeFET)-based memory array comprising:
a semiconductor substrate;
an array of channel structures having a ferroelectric material disposed along the channel structures;
an array of gate electrode structures operatively coupled to the channel structures at discrete regions along a length of the channel structures; and
an array of source/drain electrode structures operatively coupled to the channels structures at discrete regions along a length of the channel structures,
wherein channel structures, the gate electrode structures, and the source/drain electrodes structures are substantially perpendicularly disposed with respect to each other on the semiconductor substrate, and
wherein an array of FeFETs memory cells are formed on each of the channel structures based on the discrete regions of the channel structure at which the gate electrode structures and the source/drain electrode structures are operatively coupled.

2. The memory array of claim 1 , wherein a length of the channel structures extend vertically with respect to the semiconductor substrate to form vertical columns.

3. The memory array of claim 2 , wherein a length of the gate electrode structures and the source/drain electrode structures extend horizontally with respect to the substrate to form horizontal rows.

4. The memory array of claim 2 , wherein the gate electrode structures and the source/drain electrode structures are vertically and alternatingly stacked to form layers.

5. The memory array of claim 4 , further comprising:
an isolating material disposed between adjacent layers of gate electrode structures and source/drain electrode structures.

6. The memory array of claim 1 , wherein a length of the channel structures extend horizontally with respect to the semiconductor substrate to form rows of channel structures in a vertically arranged stack.

7. The memory array of claim 6 , wherein a length of the gate electrode structures extend vertically with respect to the substrate to form vertical columns.

8. The memory array of claim 7 , wherein a length of the source/drain electrode structures extend horizontally with respect to the substrate to form horizontal rows.

9. The memory array of claim 8 , wherein the gate electrode structures and the source/drain electrode structures are alternatingly disposed along a length of the channel structures.

10. The memory array of claim 1 , further comprising:
an interfacial material disposed on along the channel structures, the interfacial material being disposed between the channel structures and the ferroelectric material.

11. The memory array of claim 1 , wherein the gate electrode structures and the source/drain electrode structures are arranged with logical AND connections.

12. A Ferroelectric Field Effect Transistor (FeFET)-based memory circuit comprising:
a plurality of FeFET-based data memory cells with logical AND connections, the FeFET-based data memory cells being arranged in a three-dimensional structure including:
an array of channel structures having a ferroelectric material disposed along the channel structures;
an array of gate electrode structures operatively coupled to the channel structures at discrete regions along a length of the channel structures; and
an array of source/drain electrode structures operatively coupled to the channels structures at discrete regions along a length of the channel structures,
wherein channel structures, the gate electrode structures, and the source/drain electrodes structures are substantially perpendicularly disposed with respect to each other on a semiconductor substrate, and
wherein the plurality of FeFETs memory cells are formed by each of the channel structures based on the discrete regions of the channel structure at which the gate electrode structures and the source/drain electrode structures are operatively coupled.

13. A method of fabricating a three-dimensional Ferroelectric Field Effect Transistor (FeFET)-based memory array, the method comprising:
a. forming an array of hardmask on a semiconductor wafer;
b. etching isotropically one line of the hardmask to form etched walls;
c. covering sides of the etched walls with a mask;
d. repeating steps b and c to obtaining a multi-layer structure; and
e. further etching or oxidizing the multi-layer structure to separate channels in a direction that is substantially perpendicular to the semiconductor wafer to form a plurality of channel structures.

14. The method of claim 13 , further comprising:
forming gate electrode structures by depositing conducting material in defined regions corresponding at which the gate electrode structures are to be formed and etching the conducting material.

15. The method of claim 13 , further comprising:
exposing separate gate windows in the multilayer structure; and
filling the separate gate windows with gate electrode material to form a plurality of gate electrode structures.

16. The method of claim 13 , further comprising:
etching the multilayer structure to form patterns in a plane that is substantially parallel to the semiconductor wafer.

17. The method of claim 13 , further comprising:
exposing separate source/drain regions; and
filling the source/drain regions with source/drain electrode material and isolation material.

18. A method of fabricating a three-dimensional Ferroelectric Field Effect Transistor (FeFET)-based memory array, the method comprising:
a. depositing channel material on a semiconductor wafer;
b. depositing isolation material on the channel material;
c. repeating steps a and b to form a multilayer structure having alternating layers of the channel material and the isolation material;
d. forming a hardmask on the multilayer structure to cover portions of the multilayer structure;
e. removing strips of the multilayer structure to define separate channel structures that extend horizontally with respect to the semiconductor wafer
f. exposing separate gate windows in the multilayer structure; and
g. filling the separate gate windows with gate electrode material to form a plurality of gate electrode structures.

19. The method of claim 18 , further comprising:
forming gate electrode structures by depositing conducting material in defined regions corresponding at which the gate electrode structures are to be formed and etching the conducting material.

20. The method of claim 18 , further comprising:
etching the multilayer structure to form patterns in a plane that is substantially parallel to the semiconductor wafer.

21. The method of claim 18 , further comprising:
exposing separate source/drain regions; and
filling the source/drain regions with source/drain electrode material and isolation material.

22. A method of fabricating a three-dimensional Ferroelectric Field Effect Transistor (FeFET)-based memory array, the method comprising:
a. depositing channel material on a semiconductor wafer;
b. depositing isolation material on the channel material;
c. repeating steps a and b to form a multilayer structure having alternating layers of the channel material and the isolation material;
d. forming a hardmask on the multilayer structure to cover portions of the multilayer structure;
e. removing strips of the multilayer structure to define separate channel structures that extend horizontally with respect to the semiconductor wafer;
f. exposing separate source/drain regions; and
g. filling t

Assignees

• Univ Yale

Inventors

• Sun Xiao
• Ma Tso-Ping

Classifications

• H10D30/0415 Primary

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/701 Primary

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• H01L29/6684 Primary

  Electricity · mapped topic

• H01L27/1159

  Electricity · mapped topic