Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-8957471-B2
Application number	US-201113051595-A
Country	US
Kind code	B2
Filing date	Mar 18, 2011
Priority date	Nov 30, 2010
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction. The semiconductor pillar is provided in a central portion of the stacked body and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode film and the semiconductor pillar.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a stacked body provided above the substrate, the stacked body including a plurality of insulating films stacked alternately with a plurality of electrode films;
conductive members connecting electrically the electrode films to the substrate;
a semiconductor pillar provided in a first portion of the stacked body and extending in a stacking direction of the insulating films and the electrode films;
a charge storage layer provided between the electrode film and the semiconductor pillar; and
a plurality of terraces being formed in each of a plurality of second portions of the stacked body, the plurality of terraces being configured with upper faces of the electrode films respectively, the plurality of terraces being arranged along only a first direction and configuring a stairstep configuration in each of the second portions, the second portions being arranged along a second direction,
each of the conductive members being lead out from each of the terraces along the second direction, and
the first direction and the second direction being parallel to the upper face of the substrate and intersecting each other,
wherein a length of the second portion in the second direction is shorter than a length of the first portion in the second direction.

2. The device according to claim 1 , wherein the conductive member electrically connects the electrode film to a source/drain region of a transistor formed in the substrate.

3. The device according to claim 1 , wherein the second portion includes a stairstep portion and a tower portion, a plurality of the terraces are formed in the stairstep portion, and all of the electrode films are stacked in the tower portion.

4. The device according to claim 3 , wherein a level of the upper face of the electrode film configures the terrace decreases as the terrace is positioned away from the first portion.

5. The device according to claim 4 , wherein the stairstep portion and the tower portion are formed over the total length of the second portion in the second direction and arranged alternately along the first direction.

6. The device according to claim 3 , wherein the stairstep portion is formed on one second-direction side of the second portion, and the tower portion is formed on one other second-direction side of the second portion.

7. The device according to claim 1 , wherein
the conductive member includes:
a via connected electrically to the upper face of the electrode film;
a contact provided on the second-direction side as viewed from the end portion, a lower end of the contact being electrically connected to the substrate; and
an interconnect electrically connecting an upper end portion of the via to an upper end portion of the contact.

8. The device according to claim 1 , further comprising:
another stacked body provided above the substrate, the other stacked body being disposed in a region apart from the stacked body in the second direction, the other stacked body including a plurality of insulating films stacked alternately with a plurality of electrode films.

9. The device according to claim 1 , wherein
the second portions are provided in an end portion of the stacked body on the first direction side.

10. A semiconductor memory device, comprising:
a substrate;
a stacked body provided above the substrate, the stacked body including a plurality of insulating films stacked alternately with a plurality of electrode films;
a conductive member connecting electrically the electrode film to the substrate;
a semiconductor pillar provided in a first portion of the stacked body and extending in a stacking direction of the insulating films and the electrode films;
a charge storage layer provided between the electrode film and the semiconductor pillar; and
a plurality of terraces being formed in a second portion of the stacked body, the plurality of terraces being configured with upper faces of the electrode films respectively, the plurality of terraces being arranged along only a first direction and configuring a stairstep configuration,
the conductive member being lead out from the terrace along a second direction, and
the first direction and the second direction being parallel to the upper face of the substrate and intersecting each other,
wherein the terraces are arranged to form a valley in the stairstep portion, a level number of the electrode film included in the terrace changes n (n being an integer not less than 2) at a time at a slope of the valley, and the level number of the electrode film included in the terrace changes only one at a time at a bottom of the valley.

11. The device according to claim 10 , wherein a plurality of the valleys are formed, and the level number of the electrode film included in the terrace changes only one at a time at a peak between the valleys.

Assignees

• Fukuzumi Yoshiaki
• Toshiba Kk

Inventors

• Fukuzumi Yoshiaki

Classifications

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L29/7926 Primary

  Electricity · mapped topic