Nonvolatile memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9245839-B2
Application number	US-201314027599-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Dec 3, 2008
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a semiconductor substrate including a memory cell region and a contact region surrounding the memory cell region;
a plurality of first pillars extending in the memory cell region perpendicular to the semiconductor substrate, the plurality of first pillars arranged in a two-dimensional array a first distance apart from one another;
a plurality of electrodes that intersect the first pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate, wherein interlayer dielectric layers separate the stacked electrodes;
a plurality of second inactive pillars in the contact region extending perpendicular to the semiconductor substrate, the second inactive pillars penetrating the at least one or more of the electrodes and the interlayer dielectric layers, wherein the second inactive pillars are spaced apart from the closest of the first pillars arranged in the two-dimensional array a greater distance than the first distance and are of a dielectric material; and
a contact plug provided on the contact region and connected to one of the electrodes, wherein the contact plug is disposed between the second inactive pillars adjacent to each other.

2. The nonvolatile memory device of claim 1 , wherein the first pillars comprise semiconductor pillars.

3. The nonvolatile memory device of claim 1 , wherein the electrodes are stacked to have a stepwise structure on the contact region.

4. The nonvolatile memory device of claim 1 , wherein the electrodes have a horizontal length decreasing with increasing vertical height from the semiconductor substrate.

5. The nonvolatile memory device of claim 1 , wherein the second pillar comprises an insulating material.

6. The nonvolatile memory device of claim 1 , further comprising another second pillar in the contact region, the another second pillar disposed immediately adjacent to the at least one second pillar, the another second pillar is shorter than the at least one second pillar.

7. The nonvolatile memory device of claim 1 , wherein a vertical length of the at least one second pillar is different from a vertical length of the first pillars.

8. The nonvolatile memory device of claim 1 , further comprising contact plugs provided on the contact region and connected to the electrodes, respectively; and
wherein the electrodes comprise sidewalls located at different horizontal positions from each other, on the contact region.

9. The nonvolatile memory device of claim 8 , wherein the at least one second pillar is disposed between the contact plugs adjacent to each other.

10. The nonvolatile memory device of claim 8 , wherein the at least one second pillar is disposed between the first pillar and the contact plugs.

11. The nonvolatile memory device of claim 1 , further comprising a data storage layer interposed between the first pillars and the electrodes.

12. The nonvolatile memory device of claim 1 , wherein the contact region is disposed around the memory cell region.

13. The nonvolatile memory device of claim 1 , wherein
the first pillars are arranged two-dimensionally on the semiconductor substrate; and
the electrodes are connected to at least four or more of the two-dimensionally arranged first pillars or to at least two or more of the one-dimensionally arranged first pillars.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chae Soodoo
• Lee Myoungbum
• Moon Huichang
• Kim Hansoo
• Kim Jingyun
• Kim Kihyun
• Choi Siyoung
• Cho Hoosung

Classifications

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title