Semiconductor device

Patent metadata

Field	Value
Publication number	US-9991265-B2
Application number	US-201615157565-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Dec 25, 2009
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a driver circuit comprising a second transistor;
an insulating layer over the second transistor;
a memory cell over the insulating layer, the memory cell comprising:
a first transistor, a channel formation region of the first transistor comprising a first oxide semiconductor layer; and
a capacitor,

wherein a gate of the first transistor is electrically connected to a word line,
wherein one of a source and a drain of the first transistor is electrically connected to a bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
wherein the other electrode of the capacitor is electrically connected to a capacitor line, and
wherein an off-state current per micrometer of a channel width of the first transistor is 100 zA/μm or less at room temperature.

2. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

3. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer comprises a crystal region.

4. The semiconductor device according to claim 1 , wherein a carrier concentration of the first oxide semiconductor layer is lower than 1×10 12 /cm 3 .

5. The semiconductor device according to claim 1 ,
wherein a channel formation region of the second transistor comprises a semiconductor material.

6. An electronic device comprising the semiconductor device according to claim 1 .

7. A semiconductor device comprising:
a driver circuit comprising a second transistor;
an insulating layer over the second transistor;
a memory cell over the insulating layer, the memory cell comprising:
a first transistor, a channel formation region of the first transistor comprising an oxide semiconductor layer; and
a capacitor comprising the oxide semiconductor layer,

wherein a gate of the first transistor is electrically connected to a word line,
wherein one of a source and a drain of the first transistor is electrically connected to a bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
wherein the other electrode of the capacitor is electrically connected to a capacitor line, and
wherein an off-state current per micrometer of a channel width of the first transistor is 100 zA/μm or less at room temperature.

8. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

9. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises a crystal region.

10. The semiconductor device according to claim 7 , wherein a carrier concentration of the oxide semiconductor layer is lower than 1×10 12 /cm 3 .

11. The semiconductor device according to claim 7 ,
wherein a channel formation region of the second transistor comprises a semiconductor material.

12. An electronic device comprising the semiconductor device according to claim 7 .

13. A semiconductor device comprising:
a driver circuit comprising a second transistor;
an insulating layer over the second transistor;
a memory cell over the insulating layer, the memory cell comprising:
a first transistor, a channel formation region of the first transistor comprising a first oxide semiconductor layer; and
a capacitor,

wherein a gate of the first transistor is electrically connected to a word line,
wherein one of a source and a drain of the first transistor is electrically connected to a bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor, and
wherein the other electrode of the capacitor is electrically connected to a capacitor line.

14. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises a crystal region.

16. The semiconductor device according to claim 13 , wherein a carrier concentration of the first oxide semiconductor layer is lower than 1×10 12 /cm 3 .

17. The semiconductor device according to claim 13 , wherein a channel formation region of the second transistor comprises a semiconductor material.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Kato Kiyoshi

Classifications

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/003

  Cell access · CPC title

• H10B10/00

  Static random access memory [SRAM] devices · CPC title

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title