Semiconductor device manufacture method

Patent metadata

Field	Value
Publication number	US-9991159-B2
Application number	US-201715449233-A
Country	US
Kind code	B2
Filing date	Mar 3, 2017
Priority date	Sep 21, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved. The method includes removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved. The method includes forming a second metal film in the second groove by the plating.

First claim

What is claimed is:

1. A semiconductor device manufacturing method comprising:
forming a sacrificial film on a material film;
processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove;
forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove;
forming a first metal film having a thickness equal to or larger than half the first width, and smaller than half the second width, on the catalyst layer by plating;
removing at least a portion of the first metal film in the second groove while leaving at least a portion of the first metal film in the first groove unremoved;
removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved; and
forming a second metal film in the second groove by plating.

2. The semiconductor device manufacturing method according to claim 1 ,
wherein the catalyst layer includes at least one of palladium, cobalt, or platinum,
the first metal film includes nickel, and
the second metal film includes copper.

3. The semiconductor device manufacturing method according to claim 1 ,
wherein the first and second metal films are formed by electroless plating using the catalyst layer.

4. The semiconductor device manufacturing method according to claim 1 , further comprising:
after forming the second metal film, removing the sacrificial film; and
forming a covering film on side surfaces of the first metal film and second metal film.

5. The semiconductor device manufacturing method according to claim 4 , further comprising
forming an organic molecular film on the sacrificial film and on the material film before forming the catalyst layer.

6. The semiconductor device manufacturing method according to claim 5 , wherein the organic molecular film is a self-assembled monolayer film.

7. The semiconductor device manufacturing method according to claim 4 ,
wherein the material film and the covering film each includes a silicon nitride film.

8. The semiconductor device manufacturing method according to claim 1 ,
wherein the sacrificial film is a photoresist film.

Assignees

• Toshiba Memory Corp

Inventors

• Ito Fuyuma
• Yoshimizu Yasuhito
• Akeboshi Yuya
• Okuchi Hisashi
• Kitamura Masayuki

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P76/202

  for lift-off processes · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title