Three-dimensional memory device with electrically isolated support pillar structures and method of making thereof

Patent metadata

Field	Value
Publication number	US-9978766-B1
Application number	US-201615347101-A
Country	US
Kind code	B1
Filing date	Nov 9, 2016
Priority date	Nov 9, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
a second tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the first tier structure;
a memory opening vertically extending through an entirety of the first tier structure and the second tier structure to a top surface of the substrate;
a support opening vertically extending through the entirety of the first tier structure and the second tier structure to the top surface of the substrate and laterally offset from the memory openings;
a memory stack structure located within the memory opening and comprising a vertical semiconductor channel that is electrically shorted to a horizontal semiconductor channel located within the substrate;
a support pillar structure located within the support opening and comprising a vertical semiconductor layer comprising a same material as the vertical semiconductor channel and a dielectric material portion that electrically isolates the vertical semiconductor layer from the substrate; and
a first epitaxial pedestal located at a bottom portion of the memory opening and contacting the vertical semiconductor channel and the substrate; and
a second epitaxial pedestal located at a bottom portion of the support opening and comprising a same material as the first epitaxial pedestal and vertically spaced from a bottommost surface of the vertical semiconductor layer,

wherein:
the first epitaxial pedestal has a greater height than the second epitaxial pedestal; and
the three-dimensional memory device comprises a feature selected from:
a first feature that the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and a subset of the first electrically conductive layers; and
a second feature that the first epitaxial pedestal has a substantially same height as the second epitaxial pedestal, and the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer.

2. The three-dimensional memory device of claim 1 , wherein:
the dielectric material portion electrically isolates the vertical semiconductor layer from horizontal semiconductor channel located within the substrate; and
a bottommost surface of the vertical semiconductor channel is more proximal to a horizontal plane including the top surface of the substrate than a bottommost surface of the vertical semiconductor layer is to the horizontal plane.

3. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the first feature.

4. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the second feature.

5. The three-dimensional memory device of claim 1 , further comprising a first semiconductor oxide portion having an annular shape and laterally surrounding a bottom portion of the vertical semiconductor channel,
wherein the dielectric material portion comprises a second semiconductor oxide portion underlying the vertical semiconductor layer having a same composition as the first semiconductor oxide portion.

6. The three-dimensional memory device of claim 5 , wherein:
the second semiconductor oxide portion has a greater height than the first semiconductor oxide portion; and
the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and a subset of the first electrically conductive layers.

7. The three-dimensional memory device of claim 5 , further comprising a metal oxide etch stop portion located above the second semiconductor oxide portion, wherein:
the second semiconductor oxide portion underlies the metal oxide etch stop portion; and
the vertical semiconductor layer vertically extends through each of the second electrically conductive layers and does not extend below a horizontal plane including a top surface of a topmost first electrically conductive layer.

8. The three-dimensional memory device of claim 5 , wherein the second semiconductor oxide portion comprises boron, phosphorus or arsenic doped silicon oxide.

9. The three-dimensional memory device of claim 1 , wherein:
the memory stack structure comprises a memory film including a first layer stack;
the support pillar structure comprises a second layer stack, wherein each layer within the second layer stack has a same thickness and a same material composition as a corresponding layer within the first layer stack; and
a bottommost surface of the second layer stack contacts a top surface of the dielectric material portion.

10. The three-dimensional memory device of claim 9 , wherein the top surface of the dielectric material portion is located between a topmost layer among the first electrically conductive layers and a bottommost layer among the first electrically conductive layers.

11. The three-dimensional memory device of claim 9 , wherein:
the top surface of the dielectric material portion is within a same horizontal plane as an interface between the first tier structure and the second tier structure; and
the dielectric material portion comprises a dielectric metal oxide etch stop portion.

12. The three-dimensional memory device of claim 11 , further comprising a support opening fill material portion and an epitaxial pedestal located within the support opening and underlying the dielectric material portion.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the first and second electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

14. A three-dimensional memory device comprising:
a first tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;
a second tier structure comprising

Assignees

• Sandisk Technologies Llc

Inventors

• Hosoda Naohiro
• Kawamura Takeshi
• Furihata Yoko
• Funayama Kota

Classifications

• H01L27/11556 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11517

  Electricity · mapped topic