Three dimensional NAND device with channel contacting conductive source line and method of making thereof

Patent metadata

Field	Value
Publication number	US-9455263-B2
Application number	US-201414317274-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Jun 27, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.

First claim

What is claimed is:

1. A monolithic three dimensional NAND string, comprising:
a NAND memory cell region of a NAND device, comprising a conductive source line that extends substantially parallel to a major surface of a substrate, and a semiconductor channel that extends substantially perpendicular to a major surface of the substrate, wherein an element selected from the first semiconductor channel and a doped source region underlying the semiconductor channel physically contacts a sidewall of the conductive source line;
at least one memory film located adjacent to the first semiconductor channel, and
a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
a source side select transistor located between the conductive source line and the plurality of control gate electrodes;
a drain side select transistor located over the NAND memory cell region; and
a drain line which electrically contacts a drain region in an upper portion of the first semiconductor channel.

2. The monolithic three dimensional NAND string of claim 1 , wherein the conductive source line comprises a metal, a metal alloy, or a doped semiconductor.

3. The monolithic three dimensional NAND string of claim 1 , wherein the semiconductor channel comprises amorphous silicon or polysilicon having a first conductivity type, the conductive source line comprises single crystal silicon or polysilicon having a second conductivity type and a higher doping concentration than the semiconductor channel, and the substrate comprises a single crystal silicon substrate having a lower doping concentration than the conductive source line.

4. The monolithic three dimensional NAND string of claim 1 , wherein the conductive source line comprises tungsten or ruthenium.

5. The monolithic three dimensional NAND string of claim 1 , wherein the element is the doped source region.

6. The monolithic three dimensional NAND string of claim 1 , wherein the first semiconductor channel comprises an epitaxial, single crystal silicon pillar located on the major surface of the substrate.

7. The monolithic three dimensional NAND string of claim 1 , further comprising a silicon contact layer located between the conductive source line and the first semiconductor channel.

8. The monolithic three dimensional NAND string of claim 1 , further comprising an insulating layer located between a silicon portion of the substrate and the conductive source line.

9. The monolithic three dimensional NAND string of claim 1 , wherein the at least one memory film comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric, and the memory film is located between the first semiconductor channel and the plurality of control gate electrodes.

10. The monolithic three dimensional NAND string of claim 9 , wherein:
the tunnel dielectric comprises a layer comprising silicon oxide or an ONO stack which extends perpendicular to the major surface of the substrate;
the charge trapping layer comprises a silicon nitride layer which extends perpendicular to the major surface of the substrate and which contacts the tunnel dielectric; and
the blocking dielectric comprises a layer which either extends perpendicular to the major surface of the substrate and which contacts the charge trapping layer, or has a plurality of regions each surrounding a respective one of the plurality of control gate electrodes.

11. The monolithic three dimensional NAND string of claim 10 , wherein:
the substrate comprises a silicon substrate;
the NAND string is located in a monolithic, three dimensional array of NAND strings located over the silicon substrate;
at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

12. A memory block, comprising:
an array comprising at least one row of monolithic three dimensional NAND strings of claim 9 ;
a first dielectric filled trench located on a first side of the array;
a first source electrode located in the first dielectric filled trench and extending substantially perpendicular to the major surface of the substrate, wherein a bottom portion of the first source electrode contacts the conductive source line; and
a second dielectric filled trench located on a second side of the array opposite to the first side of the array.

13. The memory block of claim 12 , wherein:
the at least one row of monolithic three dimensional NAND strings comprises at least a 4×4 array of monolithic three dimensional NAND strings;
a second source electrode located in the second dielectric filled trench and extending substantially perpendicular to the major surface of the substrate, wherein a bottom portion of the second source electrode contacts the conductive source line;
a plurality of drain lines are located over the array;
the first control gate electrode is continuous in the array;
the second control gate electrode is continuous in the array;
the source side select transistor comprises a select gate electrode, and the select gate electrode is continuous in the array; and
all of the monolithic three dimensional NAND strings in the array are configured to be erased together in the same erase step.

14. The memory block of claim 13 , wherein the erase step comprises a well erase or a gate induced drain leakage erase.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Shoji Go
• Alsmeier Johann
• Pachamuthu Jayavel
• Dong Yingda
• Yuan Jiahui

Classifications

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H01L27/11582

  Electricity · mapped topic