High dielectric constant etch stop layer for a memory structure

Patent metadata

Field	Value
Publication number	US-9230979-B1
Application number	US-201414530220-A
Country	US
Kind code	B1
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 is formed a substrate. A stack of alternating layers comprising first material layers and second material layers is formed over the high-k dielectric material layer. A memory opening is formed through the stack employing a top surface of the high-k dielectric material layer as an etchstop layer, thereby minimizing an overetch. A memory film and a semiconductor channel are subsequently formed. During formation of a backside contact trench, the high-k dielectric material layer can be employed as an etch stop layer. Thus, the high-k dielectric material layer can be employed as a common etch stop layer for formation of the memory opening and the backside contact trench.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 and located over a substrate;
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over the high-k dielectric material layer;
a memory opening extending through the stack; and
a memory film and a semiconductor channel located within the memory opening, wherein:
the memory film is in contact with a top surface of the high-k dielectric material layer; and
a portion of the semiconductor channel extends through an opening in the high-k dielectric material layer and contacts a semiconductor material within the substrate.

2. The monolithic three-dimensional memory device of claim 1 , wherein the high-k dielectric material layer comprises a dielectric metal oxide.

3. The monolithic three-dimensional memory device of claim 1 , wherein the high-k dielectric material layer comprises an aluminum oxide layer.

4. The monolithic three-dimensional memory device of claim 1 , wherein the high-k dielectric material layer is a horizontal layer having a topmost surface located below a horizontal plane including a top surface of a bottommost electrically conductive layer within the stack.

5. The monolithic three-dimensional memory device of claim 1 , wherein the memory film comprises a blocking dielectric layer extending through the stack and including a horizontal portion having a bottom surface that contacts a top surface of the high-k dielectric material layer.

6. The monolithic three-dimensional memory device of claim 5 , wherein a sidewall of the high-k dielectric material layer at the opening is vertically coincident with a sidewall of the blocking dielectric layer.

7. The monolithic three-dimensional memory device of claim 5 , wherein the memory film further comprises a plurality of blocking dielectric portions having an annular shape, contacting the blocking dielectric layer, and surrounding the blocking dielectric layer.

8. The monolithic three-dimensional memory device of claim 7 , wherein a periphery of the high-k dielectric material layer is laterally recessed inward from an outer sidewall of a bottommost blocking dielectric portion among the plurality of blocking dielectric portions.

9. The monolithic three-dimensional memory device of claim 5 , wherein the memory film further comprises:
at least one charge storage element located on an inner sidewall of the blocking dielectric layer; and
a tunneling dielectric contacting the at least one charge storage element and the semiconductor channel.

10. The monolithic three-dimensional memory device of claim 1 , wherein a sidewall of the semiconductor channel is in contact with a sidewall of the high-k dielectric material layer at the opening.

11. The monolithic three-dimensional memory device of claim 1 , further comprising:
a source region located within the substrate; and
a source contact via structure extending through the stack and contacting the source region.

12. The monolithic three-dimensional memory device of claim 11 , further comprising an insulating spacer extending through the stack and laterally surrounding the source contact via structure.

13. The monolithic three-dimensional memory device of claim 12 , further comprising at least one backside blocking dielectric layer contacting each of the electrically conductive layers and the insulating spacer.

14. The monolithic three-dimensional memory device of claim 13 , wherein the backside blocking dielectric layer comprises a silicon oxide layer.

15. The monolithic three-dimensional memory device of claim 13 , wherein the backside blocking dielectric layer comprises an additional high-k dielectric material layer.

16. The monolithic three-dimensional memory device of claim 12 , further comprising a dielectric pad layer located over the substrate and including an opening therein, wherein the insulating spacer contacts a sidewall of the opening of the dielectric pad layer.

17. The monolithic three-dimensional memory device of claim 16 , wherein the sidewall of the opening of the dielectric pad layer is vertically coincident with an inner sidewall of the insulating spacer.

18. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region; and
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

19. The three-dimensional memory device of claim 18 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack are in electrical contact with the plurality of control gate electrode and extend from the device region to a contact region including the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

20. A method of manufacturing a three-dimensional memory structure, comprising:
forming a high dielectric constant (high-k) dielectric material layer having a dielectric constant greater than 7.9 over a substrate;
forming a stack of alternating layers comprising first material layers and second material layers over the high-k dielectric material layer;
forming a memory opening through the stack employing the high-k dielectric material layer as an etchstop layer;
forming a memory film in the memory opening;
forming an extension of the memory opening by an anisotropic etch of the high-k dielectric material layer employing at least the memory film as an etch mask, wherein the extension of the memory opening extends to the substrate; and
forming a semiconductor channel on the memory film, wherein the semiconductor channel extends through the extension opening in the high-k dielectric material layer and contacts the substrate.

21. The method of claim 20 , further comprising forming a backside opening through the stack employing the high-k dielectric material layer as an etchstop layer.

22. The method of claim 20 , wherein the memory film is formed directly on a top surface of the high-k dielectric material layer.

23. The method of claim 20 , wherein forming the high-k dielectric material layer comprises depositing a dielectric metal oxide layer.

24. The method of claim 20 , wherein forming the high-k dielectric material layer comprises depositing an aluminum oxide layer.

25. The method of claim 20 , wherein a bottommost surface of the stack is formed on a topmost surface of the high-k dielectric material layer.

26. The method of claim 20 , wherein forming the memory film comprises forming a blocking dielectric layer dire

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Pachamuthu Jayavel
• Alsmeier Johann

Classifications

• H10P50/283

  by chemical means · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L21/31144

  Electricity · mapped topic

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic