Methods of fabricating a three-dimensional non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9230973-B2
Application number	US-201414264262-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Sep 17, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

First claim

What is claimed is:

1. A method of fabricating a memory device, comprising:
forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate;
removing a portion of the first stack to form a first trench;
filling the trench with a sacrificial material;
forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material;
removing a portion of the second stack to the sacrificial material to form a second trench;
removing the sacrificial material to form a continuous trench through the first stack and the second stack; and
forming a select line comprising an electrically conductive material in the continuous trench.

2. The method of claim 1 , wherein removing a portion of the first stack to form the first trench comprises etching the alternating layers of the first material and the second material to form a pair of first trench sidewalls in the first stack extending from a first end proximate to the substrate to a second end distal to the substrate, and a distance between the first trench sidewalls defines a width of the first trench,
and wherein removing a portion of the second stack to form the second trench comprises etching the alternating layers of the first material and the second material to the sacrificial material to form a pair of second trench sidewalls in the second stack extending from a first end proximate to the second end of the first trench to a second end distal to the second end of the first trench, and a distance between the second trench sidewalls defines a width of the second trench, and the width of the first trench at the second end of the first trench is greater than the width of the second trench at the first end of the second trench.

3. The method of claim 2 , wherein the width of the first trench decreases between the second end and the first end of the first trench.

4. The method of claim 3 , wherein the width of the first trench at the second end of the first trench is configured to compensate for misalignment of the first end of the second trench during a high aspect ratio trench etch.

5. The method of claim 2 , wherein the width of the second trench decreases between the second end and the first end of the second trench.

6. The method of claim 1 , wherein the sacrificial material comprises at least one of silicon nitride, silicon oxide, undoped carbon, doped carbon, amorphous carbon, polycrystalline carbon, and undoped polysilicon.

7. The method of claim 1 , wherein the continuous trench forms a first boundary of an active memory cell area.

8. The method of claim 7 , wherein a second continuous trench forms a second boundary of the active memory cell area.

9. The method of claim 8 , wherein the active memory cell area comprises a plurality of NAND memory strings extending through the first stack and the second stack, wherein each NAND memory string comprises:
a semiconductor channel which comprises at least a first portion that extends substantially perpendicular to a major surface of the substrate; and
at least one memory film located adjacent to the semiconductor channel.

10. The method of claim 9 , wherein the at least one memory film comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric, and the memory film is located between the semiconductor channel and at least one of the first material and the second material in the first and second stacks.

11. The method of claim 9 , wherein the memory device further comprises a second semiconductor channel portion which extends substantially parallel to the major surface of the substrate above or in the substrate.

12. The method of claim 1 , wherein the sacrificial material comprises a dielectric material.

13. The method of claim 1 , wherein the select line comprises a metal or metal nitride source line.

14. A method of fabricating a memory device, comprising:
forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate;
removing a portion of the first stack to form a first trench;
filling the trench with a sacrificial material;
forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material;
removing a portion of the second stack to the sacrificial material to form a second trench;
removing the sacrificial material to form a continuous trench through the first stack and the second stack;
wherein the continuous trench forms a first boundary of an active memory cell area;
wherein a second continuous trench forms a second boundary of the active memory cell area;
wherein the active memory cell area comprises a plurality of NAND memory strings extending through the first stack and the second stack, wherein each NAND memory string comprises:
a semiconductor channel which comprises at least a first portion that extends substantially perpendicular to a major surface of the substrate; and
at least one memory film located adjacent to the semiconductor channel:

wherein the memory device further comprises a second semiconductor channel portion which extends substantially parallel to the major surface of the substrate above or in the substrate;
wherein the second semiconductor channel portion is electrically connected to the at least one semiconductor channel in the plurality of NAND strings, and a second memory film portion extends substantially parallel to the major surface of the substrate and is located between the second semiconductor channel portion and a bottom surface of the first and second continuous trenches, the method further comprising:
etching through the bottom surface of the continuous trenches to expose the second memory film portion;
forming a sacrificial material over the sidewalls of the continuous trenches; and
etching a portion of the sacrificial material and the second memory film portion at the bottom of the continuous trenches to expose the second semiconductor channel portion.

15. The method of claim 14 , further comprising:
performing ion implantation through the continuous trenches to provide doped source regions in the second semiconductor channel portion.

16. The method of claim 15 , further comprising:
removing a remaining portion of the sacrificial material to expose the sidewalls of the continuous trenches.

17. A method of fabricating a memory device, comprising:
forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate;
removing a portion of the first stack to form a first trench;
filling the trench with a sacrificial material;
forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material;
removing a portion of the second stack to the sacrificial material to form a second trench;
removing the sacrificial material to form a continuous trench through the first stack and the second stack;
wherein the continuous trench forms a first boundary of an active memory cell area;
wherein a second continuous trench forms a second boundary of the active memory cell area;
wherein the active memory cell area comprises a plurality of NAND memory strings extending through the first stack and the second stack, wherein each NAND memory string comprises:
a semiconductor channel which comprises at least a first portion that extends substantially perpendicular to a

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Pachamuthu Jayavel
• Alsmeier Johann
• Makala Raghuveer S
• Lee Yao-Sheng

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title