Method and apparatus for calculating delay timing values for an integrated circuit design

Patent metadata

Field	Value
Publication number	US-9977849-B2
Application number	US-201314759232-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 9, 2013
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.

First claim

The invention claimed is:

1. A method of calculating delay timing values for an integrated circuit, IC, design, the method comprising:
applying, by a processing device, a first Negative/Positive Bias Temperature Instability, N/PBTI, compensation margin to delay values for elements within the IC design, wherein the N/PBTI compensation margin is an increase in the delay values;
calculating setup/hold timing values for timing paths within the IC design based at least partly on delay values to which the first N/PBTI compensation margin has been applied;
identifying, by the processing device, a lower-rate switching element within the IC design, wherein the lower-rate switching element has a lower switching rate than a switching rate of other switching elements in the IC design;
identifying, by the processing device, that the lower-rate switching element is a timing critical element within the IC design;
identifying timing critical elements based at least partly on the calculated setup/hold timing values; and
applying, by the processing device, an increased N/PBTI compensation margin to a delay value for the identified timing critical elements and the identified lower-rate switching element in response to the lower-rate switching element being a timing critical element, wherein the IC design is provided for manufacturing of an IC device.

2. The method of claim 1 , wherein the method comprises:
applying a test suite to the IC design;
monitoring switching activity of an element of the IC design during running of the test suite; and
identifying the lower-rate switching element based on the switching activity of the element of the IC design.

3. The method of claim 2 , wherein the method comprises:
identifying the lower-rate switching element if an element comprises an average toggle rate of less than a threshold rate.

4. The method of claim 3 , wherein the threshold rate comprises a toggle rate of less than one third of an operating frequency of the IC design.

5. The method of claim 4 , wherein the threshold rate comprises a toggle rate of less than one quarter of the operating frequency of the IC design.

6. The method of claim 5 , wherein the threshold rate comprises a toggle rate of less than one fifth of the operating frequency of the IC design.

7. The method of claim 1 , wherein the first N/PBTI compensation margin comprises a margin equal to 50% of the increased N/PBTI compensation margin.

8. The method of claim 7 , wherein the first N/PBTI compensation margin comprises a margin of between 8% and 10%, and the increased N/PBTI compensation margin comprises a margin of between 4% and 5%.

9. An apparatus comprising a processing device arranged to calculate delay timing values for an integrated circuit, IC, design, the processing device being arranged to:
apply a first Negative/Positive Bias Temperature Instability, N/PBTI, compensation margin to delay values for elements within the IC design, wherein the N/PBTI compensation margin is an increase in the delay values;
calculating setup/hold timing values for timing paths within the IC design based at least partly on delay values to which the first N/PBTI compensation margin has been applied;
identify a lower-rate switching element within the IC design;
identify that the lower-rate switching element is a timing critical element within the IC design;
identifying timing critical elements based at least partly on the calculated setup/hold timing values; and
apply an increased N/PBTI compensation margin to a delay value for the identified timing critical elements and the identified lower-rate switching element in response to the lower-rate switching element being a timing critical element, wherein the IC design is provided for manufacturing of an IC device.

10. The apparatus of claim 9 , wherein the processing device further to identify the lower-rate switching element if an element comprises an average toggle rate of less than a threshold rate.

11. The apparatus of claim 10 , wherein the threshold rate comprises a toggle rate of less than one third of an operating frequency of the IC design.

12. The apparatus of claim 9 , wherein the processing device further to apply a test suite to the IC design, to monitor switching activity of an element of the IC design during running of the test suite, and to identify the lower-rate switching element based on the switching activity of the element of the IC design.

13. A non-transitory computer program product having executable program code stored therein for calculating delay timing values for an integrated circuit, IC, design, the program code operable for:
applying a first Negative/Positive Bias Temperature Instability, N/PBTI, compensation margin to delay values for elements within the IC design, wherein the N/PBTI compensation margin is an increase in the delay values;
calculating setup/hold timing values for timing paths within the IC design based at least partly on delay values to which the first N/PBTI compensation margin has been applied;
identifying a lower-rate switching element within the IC design;
identifying that the lower-rate switching element is a timing critical element within the IC design;
identifying timing critical elements based at least partly on the calculated setup/hold timing values; and
applying an increased N/PBTI compensation margin to a delay value for the identified timing critical elements and the identified lower-rate switching element in response to the lower-rate switching element being a timing critical element, wherein the IC design is provided for manufacturing of an IC device.

14. The non-transitory computer program product of claim 13 , wherein program code operable for:
identifying the lower-rate switching element if an element comprises an average toggle rate of less than a threshold rate.

15. The non-transitory computer program product of claim 13 , wherein the threshold rate comprises a toggle rate of less than one third of an operating frequency of the IC design.

16. The non-transitory computer program product of claim 13 , wherein program code operable for:
applying a test suite to the IC design;
monitoring switching activity of an element of the IC design during running of the test suite; and
identifying the lower-rate switching element based on the switching activity of the element of the IC design.

Assignees

• Sofer Sergey
• Berkovitz Asher
• Priel Michael
• Nxp Usa Inc

Inventors

• Sofer Sergey
• Berkovitz Asher
• Priel Michael

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F17/5031 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic