Method and apparatus for calculating delay timing values for an integrated circuit design
US-9977849-B2 · May 22, 2018 · US
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Patent family 51166563
This patent family groups 2 related publications across US. Members often share priority claims or equivalent filings in different countries.
| Field | Value |
|---|---|
| Family ID | 51166563 |
| Family type | — |
| Earliest priority | Jan 9, 2013 |
| First filing country | US |
| Member publications | 2 |
| Countries | US |
| Representative publication | US9977849B2 — Method and apparatus for calculating delay timing values for an integrated circuit design |
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US9977849B2 — Method and apparatus for calculating delay timing values for an integrated circuit design (published May 22, 2018)
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