Method and system for checking the inter-chip connectivity of a three-dimensional integrated circuit
US-8972916-B1 · Mar 3, 2015 · US
Systems and methods for determining effective capacitance to facilitate a timing analysis
US9104835B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104835-B2 |
| Application number | US-201414562793-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 8, 2014 |
| Priority date | Oct 11, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for timing analysis using a processor, comprising: using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and one of the group consisting of a second ILV and a device as a function of at least different frequency values, wherein the impedance profile includes a plurality of impedance values corresponding to respective frequency values; determining an effective capacitance value corr…
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- G06F30/398Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F17/5081Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104835B2 cover?
- A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to eac…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F30/398. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).