Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
US9104834B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104834-B2 |
| Application number | US-201414514919-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 15, 2014 |
| Priority date | Jan 7, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.
Opening claim text (preview).
What is claimed: 1. A method, comprising: establishing a path selection to test; determining a process corner for each chip; measuring at least one of a path delay and a frequency of each chip; comparing data sensitivities based on a regression analysis with timing sensitivities; and adjusting a timing margin setting based on the comparison of the data sensitivities and the timing sensitivities. 2. The method of claim 1 , wherein path selection crite…
Physics · mapped topic
Physics · mapped topic
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