Chip mode isolation and cross-talk reduction through buried metal layers and through-vias

Patent metadata

Field	Value
Publication number	US-9397283-B2
Application number	US-201514610411-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Mar 15, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.

First claim

What is claimed is:

1. A chip surface base device, comprising:
a first substrate;
a plurality of vias formed in the first substrate, wherein the plurality of vias is etched into a surface of the first substrate;
metal fillings deposited into the plurality of vias;
a second substrate bonded with the first substrate, wherein the metal fillings are exposed, wherein the second substrate is bonded with the first substrate includes a metal layer between the second substrate and the first substrate;
a qubit circuit, wherein the qubit circuit is on the first substrate and is coupled to a plurality of chip modes, the plurality of chip modes operative to conduct into the metal fillings deposited into the plurality of vias and define a short into the metal layer between the second substrate and the first substrate, wherein the plurality of chip modes have wavelengths longer than distances between vias in the plurality of vias; and
wherein the plurality of vias is arranged in a location on the first substrate such that the plurality of vias isolates the plurality of chip modes between the plurality of vias and the metal layer between the second substrate and the first substrate.

2. The device of claim 1 , wherein the first and second substrates are selected to reduce dielectric loss tangent at superconducting temperatures.

3. The device of claim 2 , wherein the first and second substrates are selected to be etched selectively for subsequent qubit circuit fabrication.

4. The device of claim 1 , further comprising a metal deposited on at least one of the first and second substrates.

5. The device of claim 4 , wherein the metal is a same material as the metal fillings.

6. The device of claim 5 , wherein the metal and the metal fillings are a superconducting material.

7. The device of claim 4 , wherein the metal and the metal fillings are electrically coupled.

8. The device of claim 4 , wherein the metal is buried between the first and second substrates.

9. A chip surface base device, comprising:
a first and second substrate;
a metal deposited on at least one of the first and second substrates, the first and second substrates bonded to one another, wherein the second substrate is bonded with the first substrate includes a metal layer between the second substrate and the first substrate;
a plurality of vias in the first substrate, wherein the plurality of vias is etched into a surface of the first substrate;
metal fillings deposited into the plurality of vias, wherein the metal fillings are exposed;
a qubit circuit, wherein the qubit circuit is on the first substrate and is coupled to a plurality of chip modes, the plurality of chip modes operative to conduct into the metal fillings deposited into the plurality of vias and define a short into the metal layer between the second substrate and the first substrate, wherein the plurality of chip modes have wavelengths longer than distances between vias in the plurality of vias; and
wherein the plurality of vias is arranged in a location on the first substrate such that the plurality of vias isolates the plurality of chip modes between the plurality of vias and the metal layer between the second substrate and the first substrate.

10. The device of claim 9 , wherein the first and second substrates are selected to reduce dielectric loss tangent at superconducting temperatures.

11. The device of claim 10 , wherein the first and second substrates are selected to be etched selectively for subsequent qubit circuit fabrication.

12. The device of claim 9 , wherein the metal is a same material as the metal fillings.

13. The device of claim 9 , wherein the metal and the metal fillings are a superconducting material.

14. The device of claim 9 , wherein the metal and the metal fillings are electrically coupled.

15. The device of claim 9 , wherein the metal is buried between the first and second substrates.

Assignees

• IBM

Inventors

• Abraham David W
• Keefe George A
• Lavoie Christian
• Rothwell Mary E

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/4484

  Superconducting materials · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title