Semiconductor chip with redundant thru-silicon-vias

Patent metadata

Field	Value
Publication number	US-9437561-B2
Application number	US-87854210-A
Country	US
Kind code	B2
Filing date	Sep 9, 2010
Priority date	Sep 9, 2010
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

First claim

What is claimed is:

1. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends;
forming conductive via extensions on each of the first ends of the first conductive vias; and
forming a first conductor pad in ohmic contact with the conductive via extensions.

2. The method of claim 1 , comprising forming a second plurality of conductive vias in the layer, the second plurality of conductive vias including third ends and fourth ends, and forming a second conductor pad in ohmic contact with the third ends.

3. The method of claim 1 , comprising forming a conductor structure in ohmic contact with the second ends of the first plurality of conductive vias.

4. The method of claim 3 , wherein the conductor structure comprises a redistribution layer structure.

5. The method of claim 1 , comprising coupling an input/out structure to the first conductor pad.

6. The method of claim 5 , wherein the input/output structure comprises a solder bump or a conductive pillar.

7. The method of claim 1 , comprising stacking a second semiconductor chip on the first semiconductor chip.

8. The method of claim 1 , comprising mounting the first semiconductor chip on a circuit board.

9. The method of claim 1 , wherein the first plurality of conductive vias are formed by forming trenches in the first semiconductor chip and placing conductor material in the trenches.

10. The method of claim 1 , wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.

11. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends, the first semiconductor chip having a first side and a second and opposite side;
forming conductive via extensions on each of the first ends of the first conductive vias;
forming a first conductor structure proximate the first side and in ohmic contact with the conductive via extensions; and
forming a second conductor proximate the second side and in ohmic contact with the second ends of the first plurality of conductive vias.

12. The method of claim 11 , wherein the first conductor comprises a conductor pad and the second conductor comprises a redistribution layer structure.

13. The method of claim 11 , comprising coupling an input/output structure to the first conductor.

14. The method of claim 13 , wherein the input/output structure comprises a solder bump or a conductive pillar.

15. The method of claim 11 , comprising stacking a second semiconductor chip on the first semiconductor chip.

16. The method of claim 11 , wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.

17. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends, second ends, a polymer core and a conductor jacket around the polymer core; and
forming a first conductor pad in ohmic contact with the first ends of the first conductive vias.

Assignees

• Black Bryan
• Su Michael Z
• Refai-Ahmed Gamal
• Siegel Joe
• Prejean Seth
• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Black Bryan
• Su Michael Z
• Refai-Ahmed Gamal
• Siegel Joe
• Prejean Seth

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title