Conductive contacts having varying widths and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-9953939-B2
Application number	US-201615356316-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Sep 18, 2012
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

First claim

What is claimed is:

1. A method comprising:
forming a contact element over a substrate;
forming one or more insulating layers over the contact element;
patterning an opening in the one or more insulating layers to expose the contact element;
electrically coupling an under bump metallurgy (UBM) feature with the contact element; and
forming a conductive pillar on an opposing side of the UBM feature as the contact element, wherein a diameter of the conductive pillar at a surface of the one or more insulating layers opposite the contact element is greater than a width of the contact element, wherein the conductive pillar continuously decreases in diameter from a top surface of the UBM feature to a top surface of the conductive pillar, and wherein sidewalls of the conductive pillar are non-perpendicular to a major surface of the substrate.

2. The method of claim 1 further comprising disposing a solder joint on the top surface of the conductive pillar.

3. The method of claim 2 further comprising bonding the solder joint to a substrate trace of a semiconductor device.

4. The method of claim 2 , wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM feature is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM feature.

5. The method of claim 1 , wherein electrically coupling the UBM feature comprises disposing at least a portion of the UBM feature in the opening.

6. The method of claim 1 , wherein the one or more insulating layers comprises a first insulating layer in direct contact with the contact element and a second insulating layer in direct contact with the first insulating layer, wherein the second insulating layer is disposed between the first insulating layer and the UBM, and wherein a first portion of the opening in the second insulating layer at an interface between the first insulating layer and the second insulating layer is wider than a second portion of the opening in the first insulating layer at the interface between the first insulating layer and the second insulating layer.

7. A method comprising:
forming an under bump metallurgy (UBM) on a conductive contact pad disposed between the UBM and a semiconductor substrate; and
disposing a conductive contact element on an opposing side of the UBM as the conductive contact pad, wherein the conductive contact element comprises:
a first portion disposed in a passivation layer between the UBM and the conductive contact pad, the first portion having a first diameter,
a second portion extending through an opening in an insulating layer disposed between the passivation layer and the UBM, wherein the second portion has a second diameter different than the first diameter, and
a third portion extending farther from the semiconductor substrate than the insulating layer, the third portion having a diameter that changes from a third diameter at a surface of the UBM farthest from the semiconductor substrate to a fourth diameter less the third diameter, the fourth diameter being measured at a surface of the conductive contact element opposite the UBM, the fourth diameter is equal to a fifth diameter of the opening in the insulating layer.

8. The method of claim 7 , wherein the second diameter is greater than the first diameter.

9. The method of claim 7 , wherein the UBM extends through the passivation layer and the insulating layer.

10. The method of claim 7 , wherein a portion of the UBM is disposed between the conductive contact element and the insulating layer along a line perpendicular to a major surface of the semiconductor substrate.

11. The method of claim 7 , further comprising disposing a solder region in contact with the third portion of the conductive contact element.

12. The method of claim 11 , wherein a sidewall of the third portion comprises a substantially linear profile extending from the UBM to the solder region.

13. A device comprising:
a contact element disposed over a substrate;
a passivation layer overlying the substrate and in direct contact with the contact element, the passivation layer having a first opening therein, the first opening having a first diameter at a surface of the passivation layer opposite the contact element;
an insulating layer overlying and in direct contact with the passivation layer, the insulating layer having a second opening therein, the second opening having a second diameter at an interface between the insulating layer and the passivation layer, the second diameter being different than the first diameter;
an under bump metallurgy (UBM) lining the first opening and the second opening and electrically coupled with the contact element;
a conductive pillar on the UBM, wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM; and
a substrate trace bonded to the conductive pillar by a solder joint.

14. The device of claim 13 , wherein a distance between the substrate trace and an adjacent substrate trace is less than a distance between the conductive pillar and an adjacent conductive pillar, the adjacent conductive pillar being bonded to the adjacent substrate trace by an additional solder joint.

15. The device of claim 13 , wherein the solder joint is disposed on a top surface and sidewalls of the substrate trace.

16. The device of claim 13 , wherein the insulating layer is a polyimide layer, and wherein the conductive pillar is a copper pillar.

17. The device of claim 13 , wherein a portion of the conductive pillar extending past the insulating layer comprises a truncated-cone shape.

18. The method of claim 6 , wherein a sidewall of the first insulating layer is substantially perpendicular to a major surface of the substrate, and wherein a sidewall of the second insulating layer is substantially perpendicular to the major surface of the substrate.

19. The method of claim 7 , wherein the third diameter is equal to a width of the conductive contact pad.

20. The device of claim 13 , wherein the UBM forms an interface with a lateral surface of the passivation layer opposite the contact element.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yen-Liang
• Tseng Yu-Jen
• Huang Chang-Chia
• Kuo Tin-Hao
• Chen Chen-Shien

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title