Three-dimensional chip stack and method of forming the same

Patent metadata

Field	Value
Publication number	US-9355980-B2
Application number	US-201314016966-A
Country	US
Kind code	B2
Filing date	Sep 3, 2013
Priority date	Sep 3, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

First claim

What is claimed is:

1. A three-dimensional chip stack, comprising:
a first chip comprising a first substrate;
a first conductive pillar overlying the first substrate;
a second chip comprising a second substrate;
a second conductive pillar overlying the second substrate; and
a metallization layer between the first conductive pillar and the second conductive pillar, the metallization layer having a first surface and a second surface;
wherein the first chip is bonded to the second chip to form a bonded interconnection between the first substrate and the second substrate,
wherein the bonded interconnection comprises a first joint structure between the first conductive pillar and the first surface of the metallization layer, and a second joint structure between the second conductive pillar and the second surface of the metallization layer;
wherein the first joint structure comprises a first intermetallic compound (IMC) and the second joint structure comprises a second IMC; and
wherein the metallizaton layer has a higher melting point than the first joint structure or the second joint structure.

2. The three-dimensional chip stack of claim 1 , wherein the metallization layer comprises at least one of copper or a layer of elemental copper.

3. The three-dimensional chip stack of claim 1 , wherein at least one of the first IMC or the second IMC comprises copper and tin.

4. The three-dimensional chip stack of claim 1 , wherein:
the metallization layer comprises a first material having a first melting point;
the first IMC comprises a second material having a second melting point, the second melting point lower than the first melting point; and
the second IMC comprises a third material having a third melting point, the third melting point lower than the first melting point.

5. The three-dimensional chip stack of claim 1 , wherein the first conductive pillar comprises a copper pillar.

6. The three-dimensional chip stack of claim 5 , wherein the first conductive pillar comprises a metal capping layer on the copper pillar.

7. The three-dimensional chip stack of claim 6 , wherein the metal capping layer comprises a nickel layer.

8. The three-dimensional chip stack o of claim 7 , wherein the first IMC region comprises copper, tin and nickel.

9. The three-dimensional chip stack of claim 1 , wherein the second conductive pillar comprises a copper pillar.

10. The three-dimensional chip stack of claim 9 , wherein the second conductive pillar comprises a metal capping layer on the copper pillar.

11. The three-dimensional chip stack of claim 10 , wherein the metal capping layer comprises a nickel layer.

12. The three-dimensional chip stack o of claim 11 , wherein the second IMC region comprises copper, tin and nickel.

13. A method of forming a three-dimensional chip stack, the method comprising:
forming a first bump structure on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar;
forming a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer;
attaching the first bump structure to the second bump structure; and
performing a thermal reflow process to form a first joint structure comprising a first intermetallic compound (IMC) region between the first conductive pillar and a first surface of the metallization layer, and a second joint structure comprising a second IMC region between the second conductive pillar and a second surface of the metallization layer, wherein the metallization layer has a higher melting point than the first IMC or the second IMC.

14. The method of claim 13 , wherein the metallization layer comprises a copper layer, and the first IMC region comprises copper and tin.

15. The method of claim 13 , wherein the first conductive pillar comprises a copper pillar.

16. The method of claim 15 , wherein the first conductive pillar comprises a metal capping layer between the copper pillar and the first solder layer.

17. The method of claim 16 , wherein the metal capping layer comprises a nickel layer.

18. The method of claim 13 , further comprising forming the first solder layer as a hemisphere-shaped solder layer before attaching the first bump structure to the second bump structure.

19. A method of forming a three-dimensional chip stack, the method comprising:
receiving a first chip comprising a first bump structure formed on a first semiconductor substrate, wherein the first bump structure comprises a first conductive pillar and a first solder layer on top of the first conductive pillar;
receiving a second chip comprising a second bump structure on a second semiconductor substrate, wherein the second bump structure comprises a second conductive pillar, a second solder layer on top of the second conductive pillar, and a metallization layer on the second solder layer, the metallization layer having a higher melting point than that of the first solder layer or the second solder layer; and
bonding the first chip to the second chip by attaching the first bump structure to the second bump structure, wherein a first joint structure comprising a first intermetallic compound (IMC) region comprising copper and tin is formed between the first conductive pillar and the first surface of the metallization layer, and a second joint structure comprising a second IMC region comprising copper and tin is formed between the second conductive pillar and a second surface of the metallization layer.

20. The method of claim 19 , wherein the metallization layer comprises a copper layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Wei-Ming
• Hsieh Cheng-Hsien
• Huang Sung-Hui
• Hsu Kuo-Ching

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/019

  of bond pads · CPC title