Semiconductor device, semiconductor device package, and lightning apparatus

Patent metadata

Field	Value
Publication number	US-9583687-B2
Application number	US-201514729619-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Nov 10, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a light emitting structure including first and second conductivity-type semiconductor layers including AlxInyGa(1−x−y)N, wherein 0≦x<1, 0≦y<1, and 0≦x+y<1, and an active layer between the first and second conductivity-type semiconductor layers; and
an interconnection bump including:
an under bump metallurgy (UBM) layer on an electrode of at least one of the first and second conductivity-type semiconductor layers, the UBM layer having a first surface opposite to a surface of the electrode and a second surface extending from an edge of the first surface and connecting to the electrode, wherein the second surface is a sloped sidewall of the UBM layer;
an intermetallic compound (IMC) on the first surface of the UBM layer;
a solder bump bonded to the UBM layer with the IMC therebetween; and
a barrier layer on the second surface of the UBM layer and substantially preventing the solder bump from diffusing into the second surface of the UBM layer.

2. The semiconductor device of claim 1 , wherein the second surface of the UBM layer has a structure slightly inclined towards the electrode from the first surface of the UBM layer.

3. The semiconductor device of claim 1 , wherein the second surface of the UBM layer is substantially perpendicular to the surface of the electrode.

4. The semiconductor device of claim 1 , wherein the UBM layer has a monolayer structure including one of a Ni layer or a Cu layer.

5. The semiconductor device of claim 1 , further comprising a passivation layer adjacent to the UBM layer on the electrode.

6. The semiconductor device of claim 5 , wherein the passivation layer is spaced apart from the UBM layer on the electrode.

7. The semiconductor device of claim 5 , wherein the passivation layer has a lower thickness than a thickness of the UBM layer.

8. A semiconductor device, comprising:
a light emitting structure having a plurality of electrodes; and
an interconnection bump on the plurality of electrodes,
wherein the interconnection bump includes:
an under bump metallurgy (UBM) layer on the electrode, the UBM layer having a first surface opposite to a surface of the electrode and a second surface extending from an edge of the first surface and connecting to the electrode, wherein the second surface is a sloped sidewall of the UBM layer;
an intermetallic compound (IMC) on the first surface of the UBM layer;
a solder bump bonded to the UBM layer with the IMC therebetween; and
a barrier layer on the second surface of the UBM layer, the barrier layer substantially preventing the solder bump from diffusing into the second surface of the UBM layer.

9. The semiconductor device of claim 8 , wherein the plurality of electrodes are along a single direction in the light emitting structure.

10. The semiconductor device of claim 8 , wherein the light emitting structure includes first and second conductivity-type semiconductor layers including AlxInyGa(1−x−y)N, wherein 0≦x<1, 0≦y<1, and 0≦x+y<1, and an active layer between the first and second conductivity-type semiconductor layers.

11. A semiconductor device package comprising:
a package main body;
a semiconductor device on the package main body; and
an encapsulating portion encapsulating the semiconductor device,
wherein the semiconductor device includes:
a light emitting structure having a plurality of electrodes; and
an interconnection bump on the plurality of electrodes,
wherein the interconnection bump includes:
an under bump metallurgy (UBM) layer on the electrode, the UBM layer having a first surface opposite to a surface of the electrode and a second surface extending from an edge of the first surface and connecting to the electrode, wherein the second surface is a sloped sidewall of the UBM layer;
an intermetallic compound (IMC) on the first surface of the UBM layer;
a solder bump bonded to the UBM layer with the IMC therebetween; and
a barrier layer on the second surface of the UBM layer, the barrier layer substantially preventing the solder bump from diffusing into the second surface of the UBM layer.

12. The package of claim 11 , wherein the encapsulating portion includes at least one type of phosphor.

13. A lighting apparatus, comprising:
a housing; and
at least one semiconductor device package in the housing,
wherein the at least one semiconductor device package includes:
a package main body;
a semiconductor device on the package main body; and
an encapsulating portion encapsulating the semiconductor device,
wherein the semiconductor device includes:
a light emitting structure having a plurality of electrodes; and
an interconnection bump on the plurality of electrodes,
wherein the interconnection bump includes:
an under bump metallurgy (UBM) layer on the electrode, the UBM layer having a first surface opposite to a surface of the electrode and a second surface extending from an edge of the first surface and connecting to the electrode, wherein the second surface is a sloped sidewall of the UBM layer;
an intermetallic compound (IMC) on the first surface of the UBM layer;
a solder bump bonded to the UBM layer with the IMC therebetween; and
a barrier layer on the second surface of the UBM layer, the barrier layer substantially preventing the solder bump from diffusing into the second surface of the UBM layer.

14. The lighting apparatus of claim 13 , further comprising a cover unit in the housing and encapsulating the at least one semiconductor device package.

15. A connection bump of a semiconductor device, the connection bump comprising:
at least one under bump metallurgy (UBM) layer on an electrode of the semiconductor device;
an intermetallic compound (IMC) on the UBM layer;
a solder bump on the IMC; and
a barrier layer between a sloped sidewall of the UBM layer and the IMC, the barrier layer being configured to substantially prevent at least one of the solder bump and the IMC from diffusing into the UBM layer, the barrier layer extending between an edge of a surface of the UBM that is opposite to the electrode and the electrode.

16. The connection bump of claim 15 , wherein the barrier layer extends on a surface of the UBM layer that extends between the IMC and the electrode.

17. The connection bump of claim 15 , wherein the barrier layer has a level of wettability with respect to at least one of the IMC and the solder bump such that at least one of the IMC and the solder bump cannot be formed on the barrier layer.

18. The connection bump of claim 15 , wherein the barrier layer includes an oxide layer having at least one element of the UBM layer.

19. The connection bump of claim 15 , wherein the UBM layer comprises at least a first layer and a second layer, the first layer being in contact with the electrode.

20. The connection bump of claim 19 , wherein
the first layer includes al least titanium; and
the second layer includes at least one of nickel and copper.

Assignees

• Hwang Seok Min
• Samsung Electronics Co Ltd

Inventors

• Hwang Seok Min

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title