Bump-on-Trace Interconnect

Patent metadata

Field	Value
Publication number	US-2016190090-A1
Application number	US-201615065632-A
Country	US
Kind code	A1
Filing date	Mar 9, 2016
Priority date	Apr 18, 2012
Publication date	Jun 30, 2016
Grant date	—

Abstract

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

First claim

What is claimed is:

1 . A method comprising:
providing a first substrate having a bump disposed thereon, and the bump having a volume of conductive material disposed thereon; providing a second substrate having a conductive trace, the conductive trace having a sidewall; and mounting the first substrate on the second substrate, the mounting resulting in an electrical connection from the bump to the conductive trace, wherein the bump is separated from the conductive trace by a distance less than a height of the conductive trace, and wherein the conductive material at least partially covers a sidewall of the conductive trace.

2 . The method of claim 1 wherein:
providing a first substrate comprises forming a plurality of bumps on the first substrate, each of the plurality of bumps having a volume of conductive material disposed thereon;
providing a second substrate comprises forming a plurality of conductive traces on the second substrate; and
mounting the first substrate to the second substrate comprises electrically connecting the plurality of bumps with respective ones of the plurality of conductive traces.

3 . The method of claim 2 , wherein the conductive material is solder.

4 . The method of claim 3 , further comprising calculating a volume of solder to form a solder joint having a predetermined width.

5 . The method of claim 4 , wherein the volume of solder to form a solder joint having a predetermined width is calculated based on at least one of: a joint gap distance, a desired solder joint width, a predetermined solder joint separation, a bump geometry, a trace geometry, a minimum trace sidewall wetting region height, and a trace separation distance.

6 . The method of claim 4 , wherein the predetermined width is less than a width of the bump.

7 . The method of claim 1 , wherein a surface of the bump disposed closest to the conductive trace is wider than a surface of the conductive trace disposed closest to the bump.

8 . A method comprising:
disposing a solder joint on a bump electrically connected to a conductive land in a first substrate, wherein a first surface of the bump distal to the conductive land has a first width; aligning the first substrate to a second substrate by aligning the solder joint to a conductive trace of the second substrate; and reflowing the solder joint to bond the solder joint with the conductive trace, wherein the solder joint at least partially wets sidewalls of the conductive trace, and wherein a lateral surface of the conductive trace contacting the solder joint has a second width less than the first width.

9 . The method of claim 8 further comprising prior to reflowing the solder joint, plasma treating a surface of the conductive trace.

10 . The method of claim 8 further comprising prior to reflowing the solder joint, removing oxidation or foreign material from a surface of the conductive trace.

11 . The method of claim 8 further comprising calculating a volume of solder to form the solder joint having a predetermined width less than a width of the bump.

12 . The method of claim 8 , wherein the solder joint wets a first sidewall of the bump.

13 . The method of claim 12 , wherein in a cross-sectional view of the bump, the solder joint wets the first sidewall of the bump without wetting a second sidewall of the bump opposite the first sidewall.

14 . The method of claim 8 , wherein a second surface of the bump opposite the first surface has a second width less than the first width.

15 . The method of claim 8 , wherein a second surface of the bump opposite the first surface has a second width greater than the first width.

16 . The method of claim 8 , wherein at least a portion of the first surface of the bump is substantially free of any solder.

17 . A method comprising:
disposing a bump on a first package component, the first package component comprising:
a die substrate;
a conductive land over the die substrate; and
a dielectric layer over and covering edges of the conductive land, wherein the bump is disposed over and electrically connected to the conductive land, wherein a surface of the bump opposite the conductive land is substantially level, and wherein a sidewall of the bump is substantially straight in a cross-sectional view of the bump;
disposing a solder region on the surface of the bump opposite the conductive land; and bonding the first package component to a second package component, wherein after bonding the first package component to the second package component, a portion of the solder region is disposed on a sidewall of a conductive trace of the second package component.

18 . The method of claim 17 , wherein the surface of the bump opposite the conductive land is wider than the conductive trace.

19 . The method of claim 17 , wherein the sidewall of the bump is substantially perpendicular to a major surface of the die substrate.

20 . The method of claim 17 , wherein the sidewall of the bump is non-perpendicular to a major surface of the die substrate.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Chen Chen-Shien

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title