Overvoltage protection for a fine grained negative wordline scheme

Patent metadata

Field	Value
Publication number	US-9318162-B2
Application number	US-201414450811-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Aug 4, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

First claim

What is claimed is:

1. A circuit comprising:
a static random access memory (SRAM) cell comprising at least a wordline coupled to a plurality of NFETs of a transistor array;
a wordline driver comprising a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline, wherein overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage;
a power gating voltage circuit coupled between the wordline group decode node and the power supply;
a retention device coupled to the wordline the power supply, wherein:
the plurality of inverters of the wordline driver each include a PFET device and an NFET device;
the PFET devices are coupled to the power supply;
the NFET device of a first inverter of the plurality of inverters is coupled to a wordline pull down network and its source is coupled to the wordline;
a second inverter of the plurality of inverters is coupled to the wordline group decode node; and
in a retention state:
the wordline driver eliminates overvoltage on the NFETs of the SRAM cell;
the wordline pull down network comprises a first NFET and a second NFET, wherein the first NFET controls whether to pass a negative voltage to first node and second NFET controls whether to pass 0V (GND) onto the first node SWL; and
only one NFET will be on depending on when a retention state is on or off such that when the retention state is on the first NFET is on allowing negative voltage to pass, and the second NFET is off and when the retention state off the first NFET is off and the second NFET is on allowing 0V (GND) to pass.

2. The circuit of claim 1 , wherein in the retention state, the wordline is at negative voltage.

3. The circuit of claim 1 , wherein the retention device is a diode connected PFET.

Assignees

• IBM

Inventors

• Pilo Harold
• Wu Richard S

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/418

  Address circuits · CPC title