Overvoltage protection for a fine grained negative wordline scheme

Patent metadata

Field	Value
Publication number	US-9734891-B2
Application number	US-201514962264-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Aug 4, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

First claim

What is claimed is:

1. A circuit comprising:
a static random access memory (SRAM) cell comprising at least a wordline coupled to a plurality of NFETs of a transistor array; and
a wordline driver comprising a plurality of inverters coupled to a wordline group decode node, a power supply and the wordline, wherein overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage,
wherein:
the plurality of inverters of the word line driver are coupled to a wordline pull down network,
in a retention state, the wordline pull down network comprises a first NFET and a second NFET, wherein the first NFET controls whether to pass a negative voltage to a first node and the second NFET controls whether to pass 0V (GND) to the first node,
only one of the first NFET and the second NFET will be on depending on whether the retention state is on or off, such that, when the retention state is on the first NFET is on allowing the negative voltage to pass and the second NFET is off, and, when the retention state is off, the first NFET is off and the second NFET is on allowing 0V (GND) to pass, and
a gate of the second NFET is coupled to the word line group decode node and a gate of the first NFET is coupled to the word line group decode node through an inverter.

2. The circuit of claim 1 , further comprising a power gating voltage circuit coupled between the wordline group decode node and the power supply.

3. The circuit of claim 2 , further comprising a retention device coupled to the wordline the power supply.

4. The circuit of claim 3 , wherein:
the plurality of inverters of the wordline driver each include a PFET device and an NFET device;
the PFET devices are coupled to the power supply;
the NFET device of a first inverter of the plurality of inverters is coupled to the wordline pull down network and its source is coupled to the wordline; and
a second inverter of the plurality of inverters is coupled to the wordline group decode node.

5. The circuit of claim 4 , wherein, in a powered up state with selected wordline:
the wordline pull down network comprises a first NFET device in an OFF state and a second NFET device pulled to GND;
the PFET devices of the plurality of inverters are in an ON state;
the first NFET device of the first inverter, which is coupled to a node of the wordline pull down network, is in an OFF state; and
a supply voltage VCS is fed through the plurality of inverters to the wordline.

6. The circuit of claim 5 , wherein the supply voltage VCS is fed through the NFET device of the first inverter.

7. The circuit of claim 1 , wherein:
the plurality of inverters of the wordline driver each include a PFET device and an NFET device;
the PFET devices are coupled to the power supply;
the NFET device of a first inverter of the plurality of inverters is coupled to a wordline pull down network and its source is coupled to the wordline; and
a second inverter of the plurality of inverters is coupled to the wordline group decode node.

8. The circuit of claim 7 , wherein, in a powered up state with selected wordline:
the wordline pull down network comprises a first NFET device in an OFF state and a second NFET device pulled to GND;
the PFET devices of the plurality of inverters are in an ON state;
the first NFET device of the first inverter, which is coupled to a node of the wordline pull down network, is in an OFF state; and
a supply voltage VCS is fed through the plurality of inverters to the wordline.

9. The circuit of claim 1 , wherein, in a powered up state with selected wordline:
the wordline pull down network comprises a first NFET device in an OFF state and a second NFET device pulled to GND;
the PFET devices of the plurality of inverters are in an ON state;
the first NFET device of the first inverter, which is coupled to a node of the wordline pull down network, is in an OFF state; and
a supply voltage VCS is fed through the plurality of inverters to the wordline.

10. The circuit of claim 1 , wherein, in the retention state, the wordline driver is structured to eliminate overvoltage on the NFETs of the SRAM cell.

11. The circuit of claim 10 , wherein, in the retention state, the power supply is structured so that the wordline is at a negative voltage level.

Assignees

• IBM

Inventors

• Pilo Harold
• Wu Richard S

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title